test_compldst_multi_mmu.py: use nmigen.compat.sim

diff --git a/src/soc/experiment/test/test_compldst_multi_mmu.py b/src/soc/experiment/test/test_compldst_multi_mmu.py
index b5d6959734b0fd67ef2db27aa187a3af39f8b89a..8f5fcf1a50016cc5f74fcde268b663d00d09472d 100644 (file)
--- a/src/soc/experiment/test/test_compldst_multi_mmu.py
+++ b/src/soc/experiment/test/test_compldst_multi_mmu.py
@@ -1,7 +1,7 @@
 # test case for LOAD / STORE Computation Unit using MMU
 
 #from nmigen.compat.sim import run_simulation
-from nmigen.sim import Simulator, Delay, Settle
+from nmigen.compat.sim import Simulator, Delay, Settle
 from nmigen.cli import verilog, rtlil
 from nmigen import Module, Signal, Mux, Cat, Elaboratable, Array, Repl
 from nmigen.hdl.rec import Record, Layout