Use proper operator

diff --git a/backends/firrtl/firrtl.cc b/backends/firrtl/firrtl.cc
index 85c44824fd526c3474e9b74a41f8e98c5fabc388..76ba77abb73935fc4a9bc9fd19e4b11a22c9f41f 100644 (file)
--- a/backends/firrtl/firrtl.cc
+++ b/backends/firrtl/firrtl.cc
@@ -729,12 +729,12 @@ struct FirrtlWorker
                                        always_uint = true;
                                        firrtl_width = max(a_width, b_width);
                                }
-                               else if ((cell->type == ID($eq)) | (cell->type == ID($eqx))) {
+                               else if ((cell->type == ID($eq)) || (cell->type == ID($eqx))) {
                                        primop = "eq";
                                        always_uint = true;
                                        firrtl_width = 1;
                                }
-                               else if ((cell->type == ID($ne)) | (cell->type == ID($nex))) {
+                               else if ((cell->type == ID($ne)) || (cell->type == ID($nex))) {
                                        primop = "neq";
                                        always_uint = true;
                                        firrtl_width = 1;
@@ -759,7 +759,7 @@ struct FirrtlWorker
                                        always_uint = true;
                                        firrtl_width = 1;
                                }
-                               else if ((cell->type == ID($shl)) | (cell->type == ID($sshl))) {
+                               else if ((cell->type == ID($shl)) || (cell->type == ID($sshl))) {
                                        // FIRRTL will widen the result (y) by the amount of the shift.
                                        // We'll need to offset this by extracting the un-widened portion as Verilog would do.
                                        extract_y_bits = true;
@@ -777,7 +777,7 @@ struct FirrtlWorker
                                                firrtl_width = a_width + (1 << b_width) - 1;
                                        }
                                }
-                               else if ((cell->type == ID($shr)) | (cell->type == ID($sshr))) {
+                               else if ((cell->type == ID($shr)) || (cell->type == ID($sshr))) {
                                        // We don't need to extract a specific range of bits.
                                        extract_y_bits = false;
                                        // Is the shift amount constant?