lots of comments in the yosys script file

diff --git a/simsoc.ys b/simsoc.ys
index 0e2c880b8f9331ef20d522309984dde72a429fa2..bcdc85b1c5e8097e78c2c51490febea2d4d6caae 100644 (file)
--- a/simsoc.ys
+++ b/simsoc.ys
@@ -1,3 +1,8 @@
+# rad the main peripheral fabric, then uart16550, and finally libresoc core
+# we do not have to do include the micron ddr3 model or the lattice ecp5
+# models because apparently they're good to go, already (icarus is a lot
+# stricter than verilator, hence the munging below)
+
 read_ilang build_simsoc/top.il
 read_verilog  ../uart16550/rtl/verilog/raminfr.v
 read_verilog  ../uart16550/rtl/verilog/uart_defines.v
@@ -13,10 +18,13 @@ read_verilog  ../uart16550/rtl/verilog/uart_tfifo.v
 read_verilog  ../uart16550/rtl/verilog/uart_wb.v
 read_verilog  ./external_core_top.v
 
+# stop yosys deleting stuff
 setattr -mod -set keep 1 uart_transmitter
 setattr -mod -set keep 1 uart_receiver
 
 delete w:$verilog_initial_trigger
+
+# these are most of "proc"
 proc_prune
 proc_clean
 proc_rmdead
@@ -29,8 +37,11 @@ proc_rmdead
 proc_memwr
 proc_clean
 opt_expr -keepdc
+
+# these are important to do in this order
 memory_collect
 pmuxtree
+
 #opt_mem
 #opt_mem_priority
 #opt_mem_feedback