sim_ticks 1887184463000 # Number of ticks simulated
final_tick 1887184463000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 275099 # Simulator instruction rate (inst/s)
-host_op_rate 275099 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9249537203 # Simulator tick rate (ticks/s)
-host_mem_usage 373576 # Number of bytes of host memory used
-host_seconds 204.03 # Real time elapsed on the host
+host_inst_rate 272052 # Simulator instruction rate (inst/s)
+host_op_rate 272052 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9147074399 # Simulator tick rate (ticks/s)
+host_mem_usage 373996 # Number of bytes of host memory used
+host_seconds 206.32 # Real time elapsed on the host
sim_insts 56128524 # Number of instructions simulated
sim_ops 56128524 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.writeBursts 159652 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 25907328 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 6208 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8556800 # Total number of bytes written to DRAM
+system.physmem.bytesWritten 8555840 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 25913536 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10217728 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 97 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 25922 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 157 # Number of requests that are neither read nor write
+system.physmem.mergedWrBursts 25937 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 159 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25492 # Per bank write bursts
system.physmem.perBankRdBursts::1 25732 # Per bank write bursts
system.physmem.perBankRdBursts::2 25844 # Per bank write bursts
system.physmem.perBankRdBursts::15 25739 # Per bank write bursts
system.physmem.perBankWrBursts::0 8904 # Per bank write bursts
system.physmem.perBankWrBursts::1 8550 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9125 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8822 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9134 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8817 # Per bank write bursts
system.physmem.perBankWrBursts::4 8179 # Per bank write bursts
system.physmem.perBankWrBursts::5 8016 # Per bank write bursts
system.physmem.perBankWrBursts::6 7555 # Per bank write bursts
-system.physmem.perBankWrBursts::7 7379 # Per bank write bursts
+system.physmem.perBankWrBursts::7 7380 # Per bank write bursts
system.physmem.perBankWrBursts::8 8271 # Per bank write bursts
system.physmem.perBankWrBursts::9 7751 # Per bank write bursts
system.physmem.perBankWrBursts::10 8147 # Per bank write bursts
-system.physmem.perBankWrBursts::11 7873 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8188 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9058 # Per bank write bursts
+system.physmem.perBankWrBursts::11 7871 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8181 # Per bank write bursts
+system.physmem.perBankWrBursts::13 9046 # Per bank write bursts
system.physmem.perBankWrBursts::14 9003 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8879 # Per bank write bursts
+system.physmem.perBankWrBursts::15 8880 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 49 # Number of times write queue was full causing retry
+system.physmem.numWrRetry 48 # Number of times write queue was full causing retry
system.physmem.totGap 1887175688500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 448 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::57 209 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 146 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 154 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 162 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::55 232 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 98 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 54 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 64790 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 531.935916 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 325.040765 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 415.485108 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 531.921099 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 325.032687 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 415.479352 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 14695 22.68% 22.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 10955 16.91% 39.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 10956 16.91% 39.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5460 8.43% 48.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3097 4.78% 52.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2483 3.83% 56.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1877 2.90% 59.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1493 2.30% 61.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1431 2.21% 64.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3096 4.78% 52.80% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2482 3.83% 56.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1882 2.90% 59.53% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1491 2.30% 61.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1429 2.21% 64.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 23299 35.96% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 64790 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4900 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::196608-204799 1 0.02% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 4900 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 4900 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 27.285714 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.337905 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 63.692079 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 27.282653 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.334547 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 63.863816 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-31 4662 95.14% 95.14% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-63 56 1.14% 96.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-95 11 0.22% 96.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-127 6 0.12% 96.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-159 26 0.53% 97.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-191 25 0.51% 97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-223 16 0.33% 98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-255 2 0.04% 98.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-287 6 0.12% 98.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-95 12 0.24% 96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-127 6 0.12% 96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-159 26 0.53% 97.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-191 25 0.51% 97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-223 16 0.33% 98.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-255 3 0.06% 98.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-287 4 0.08% 98.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::288-319 8 0.16% 98.33% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::320-351 21 0.43% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-383 21 0.43% 99.18% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-415 2 0.04% 99.22% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::448-479 6 0.12% 99.35% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-511 7 0.14% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-543 9 0.18% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-575 5 0.10% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-383 20 0.41% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-415 2 0.04% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::448-479 6 0.12% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-511 7 0.14% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-543 9 0.18% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-575 6 0.12% 99.78% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::672-703 3 0.06% 99.84% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::704-735 7 0.14% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::1088-1119 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4900 # Writes before turning the bus around for reads
-system.physmem.totQLat 2145870750 # Total ticks spent queuing
-system.physmem.totMemAccLat 9735908250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2145936500 # Total ticks spent queuing
+system.physmem.totMemAccLat 9735974000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2024010000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 5301.04 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 5301.20 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 24051.04 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 24051.20 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 13.73 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 4.53 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 13.73 # Average system read bandwidth in MiByte/s
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 25.13 # Average write queue length when enqueuing
system.physmem.readRowHits 363622 # Number of row buffer hits during reads
-system.physmem.writeRowHits 110090 # Number of row buffer hits during writes
+system.physmem.writeRowHits 110075 # Number of row buffer hits during writes
system.physmem.readRowHitRate 89.83 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 82.32 # Row buffer hit rate for writes
system.physmem.avgGap 3342790.44 # Average gap between requests
system.physmem.pageHitRate 87.96 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 238971600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 130391250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.actEnergy 238979160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 130395375 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 1577557800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 431114400 # Energy for write commands per rank (pJ)
+system.physmem_0.writeEnergy 431146800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 60578040195 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1079167578750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1265384866875 # Total energy per rank (pJ)
-system.physmem_0.averagePower 670.517315 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 1795079554966 # Time in different power states
+system.physmem_0.actBackEnergy 60577818750 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1079167773000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1265384883765 # Total energy per rank (pJ)
+system.physmem_0.averagePower 670.517324 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 1795079851716 # Time in different power states
system.physmem_0.memoryStateTime::REF 63016980000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 29080496284 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 29080199534 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 250840800 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 136867500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy 250833240 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 136863375 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1579897800 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 435261600 # Energy for write commands per rank (pJ)
+system.physmem_1.writeEnergy 435132000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 123261212880 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 61601133195 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1078270137000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1265535350775 # Total energy per rank (pJ)
-system.physmem_1.averagePower 670.597050 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 1793586337716 # Time in different power states
+system.physmem_1.actBackEnergy 61600331205 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1078270840500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1265535111000 # Total energy per rank (pJ)
+system.physmem_1.averagePower 670.596923 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 1793587329216 # Time in different power states
system.physmem_1.memoryStateTime::REF 63016980000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30573727284 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30572735784 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 15007831 # Number of BP lookups
+system.cpu.branchPred.lookups 15007833 # Number of BP lookups
system.cpu.branchPred.condPredicted 13016266 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 375462 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9968114 # Number of BTB lookups
+system.cpu.branchPred.BTBLookups 9968116 # Number of BTB lookups
system.cpu.branchPred.BTBHits 5203851 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 52.204971 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 52.204960 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 809053 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 32834 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 9242509 # DTB read hits
+system.cpu.dtb.read_hits 9242504 # DTB read hits
system.cpu.dtb.read_misses 17824 # DTB read misses
system.cpu.dtb.read_acv 211 # DTB read access violations
system.cpu.dtb.read_accesses 766347 # DTB read accesses
-system.cpu.dtb.write_hits 6385998 # DTB write hits
+system.cpu.dtb.write_hits 6386002 # DTB write hits
system.cpu.dtb.write_misses 2322 # DTB write misses
system.cpu.dtb.write_acv 159 # DTB write access violations
system.cpu.dtb.write_accesses 298454 # DTB write accesses
-system.cpu.dtb.data_hits 15628507 # DTB hits
+system.cpu.dtb.data_hits 15628506 # DTB hits
system.cpu.dtb.data_misses 20146 # DTB misses
system.cpu.dtb.data_acv 370 # DTB access violations
system.cpu.dtb.data_accesses 1064801 # DTB accesses
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.numCycles 180833283 # number of cpu cycles simulated
+system.cpu.numCycles 180833533 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 56128524 # Number of instructions committed
system.cpu.committedOps 56128524 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 2493053 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.discardedOps 2493054 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 5493 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 3593535643 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 3.221772 # CPI: cycles per instruction
+system.cpu.quiesceCycles 3593535393 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 3.221776 # CPI: cycles per instruction
system.cpu.ipc 0.310388 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed
system.cpu.kern.ipl_good::22 1901 1.28% 50.68% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::31 73432 49.32% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu.kern.ipl_good::total 148896 # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks::0 1834551091000 97.21% 97.21% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::0 1834551053500 97.21% 97.21% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::21 80458000 0.00% 97.22% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::22 676198500 0.04% 97.25% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks::31 51875728000 2.75% 100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks::31 51875765500 2.75% 100.00% # number of cycles we spent at this ipl
system.cpu.kern.ipl_ticks::total 1887183475500 # number of cycles we spent at this ipl
system.cpu.kern.ipl_used::0 0.981724 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::idle 0.079943 # fraction of useful protection mode switches
system.cpu.kern.mode_switch_good::total 0.392949 # fraction of useful protection mode switches
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-system.cpu.kern.mode_ticks::user 4134630500 0.22% 2.16% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks::idle 1846457071000 97.84% 100.00% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::kernel 36591863000 1.94% 1.94% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::user 4134622500 0.22% 2.16% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks::idle 1846456980000 97.84% 100.00% # number of ticks spent at the given mode
system.cpu.kern.swap_context 4171 # number of times the context was actually changed
-system.cpu.tickCycles 84552258 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 96281025 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 1395325 # number of replacements
+system.cpu.tickCycles 84552243 # Number of cycles that the object actually ticked
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+system.cpu.dcache.tags.replacements 1395323 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.981737 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 13774282 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 1395837 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 9.868116 # Average number of references to valid blocks.
+system.cpu.dcache.tags.total_refs 13774277 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 1395835 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 9.868127 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 90985250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 511.981737 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999964 # Average percentage of cache occupancy
system.cpu.dcache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 63660758 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 63660758 # Number of data accesses
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-system.cpu.dcache.ReadReq_hits::total 7815437 # number of ReadReq hits
+system.cpu.dcache.tags.tag_accesses 63660728 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 63660728 # Number of data accesses
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system.cpu.dcache.LoadLockedReq_hits::total 182818 # number of LoadLockedReq hits
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system.cpu.dcache.WriteReq_accesses::total 6150244 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_miss_rate::total 0.133253 # miss rate for ReadReq accesses
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system.cpu.dcache.overall_miss_rate::total 0.117015 # miss rate for overall accesses
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13413.487818 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13413.487818 # average LoadLockedReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31249.754227 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_hits::total 396104 # number of demand (read+write) MSHR hits
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system.cpu.dcache.overall_mshr_hits::total 396104 # number of overall MSHR hits
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system.cpu.dcache.WriteReq_mshr_misses::total 304253 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17194 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 17194 # number of LoadLockedReq MSHR misses
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system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 1433304500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 1433304500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.119156 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.119156 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049470 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.090899 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.090899 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.090899 # mshr miss rate for overall accesses
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system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11904.835989 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11904.835989 # average LoadLockedReq mshr miss latency
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 1336266500 # number of ReadReq MSHR uncacheable cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.011265 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.833333 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2558469 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2558436 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteResp 9619 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 41593 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::UpgradeReq 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 24 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 304257 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 304257 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 16 # Transaction distribution
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system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 93421056 # Cumulative packet size per connected master and slave (bytes)
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-system.cpu.toL2Bus.snoops 41987 # Total snoops (count)
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-system.cpu.toL2Bus.snoop_fanout::stdev 0.105146 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 3693818 98.88% 98.88% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 2194690407 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 110000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
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system.iobus.reqLayer29.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer30.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer30.utilization 0.0 # Layer utilization (%)
system.iocache.overall_misses::total 173 # number of overall misses
system.iocache.ReadReq_miss_latency::tsunami.ide 21714383 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 21714383 # number of ReadReq miss cycles
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system.iocache.demand_miss_latency::tsunami.ide 21714383 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 21714383 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::tsunami.ide 21714383 # number of overall miss cycles
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::tsunami.ide 125516.664740 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 125516.664740 # average ReadReq miss latency
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system.iocache.demand_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 125516.664740 # average overall miss latency
system.iocache.overall_avg_miss_latency::tsunami.ide 125516.664740 # average overall miss latency
system.iocache.overall_avg_miss_latency::total 125516.664740 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 73082 # number of cycles access was blocked
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 10004 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.overall_mshr_misses::total 173 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 12562383 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 12562383 # number of ReadReq MSHR miss cycles
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-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 6617254811 # number of WriteInvalidateReq MSHR miss cycles
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system.iocache.demand_mshr_miss_latency::tsunami.ide 12562383 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 12562383 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::tsunami.ide 12562383 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 72614.930636 # average ReadReq mshr miss latency
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-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 159252.378008 # average WriteInvalidateReq mshr miss latency
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system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 72614.930636 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 72614.930636 # average overall mshr miss latency
system.membus.trans_dist::Writeback 118100 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 159 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 159 # Transaction distribution
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system.membus.trans_dist::ReadExReq 116519 # Transaction distribution
system.membus.trans_dist::ReadExResp 116519 # Transaction distribution
system.membus.trans_dist::BadAddressError 16 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 33098 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 32 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 920075 # Packet count per connected master and slave (bytes)
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1044879 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1044883 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44316 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30814208 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::total 30858524 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36175580 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 433 # Total snoops (count)
-system.membus.snoop_fanout::samples 565206 # Request fanout histogram
+system.membus.snoop_fanout::samples 581756 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 565206 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 581756 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 565206 # Request fanout histogram
-system.membus.reqLayer0.occupancy 30238000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 581756 # Request fanout histogram
+system.membus.reqLayer0.occupancy 30242500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 1230315562 # Layer occupancy (ticks)
+system.membus.reqLayer1.occupancy 1230317312 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 20500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 21000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2160768093 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2160772841 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 42495000 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
sim_ticks 1904437574000 # Number of ticks simulated
final_tick 1904437574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 143053 # Simulator instruction rate (inst/s)
-host_op_rate 143053 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4814720142 # Simulator tick rate (ticks/s)
-host_mem_usage 313028 # Number of bytes of host memory used
-host_seconds 395.54 # Real time elapsed on the host
+host_inst_rate 149880 # Simulator instruction rate (inst/s)
+host_op_rate 149880 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5044505517 # Simulator tick rate (ticks/s)
+host_mem_usage 380636 # Number of bytes of host memory used
+host_seconds 377.53 # Real time elapsed on the host
sim_insts 56583768 # Number of instructions simulated
sim_ops 56583768 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.demand_mshr_misses::total 1280444 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1280444 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1280444 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7039 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10032 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17071 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 28982142208 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 28982142208 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 11887451669 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31918.298557 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31918.298557 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208007.813610 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208007.813610 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 212295.504187 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 212295.504187 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 210527.531955 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210527.531955 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 911417 # number of replacements
system.cpu0.icache.tags.tagsinuse 509.418391 # Cycle average of tags in use
system.cpu1.dcache.demand_mshr_misses::total 111358 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 111358 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 111358 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 158 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2893 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 3051 # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 815361518 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 815361518 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1580599049 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21515.836913 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 21515.836913 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 185632.911392 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 185632.911392 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 218110.266160 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 218110.266160 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 216428.384136 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 216428.384136 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 211356 # number of replacements
system.cpu1.icache.tags.tagsinuse 472.195820 # Cycle average of tags in use
system.l2c.overall_mshr_misses::cpu1.inst 1677 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 11762 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 413037 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data 7039 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 158 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 7197 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data 10032 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 2893 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 12925 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data 17071 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 3051 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 20122 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 974652500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16545106250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122062750 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72786.374478 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 98564.873746 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 66350.414200 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194007.671544 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171632.911392 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193516.465194 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 199279.057018 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 204473.902523 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 200441.818182 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 197105.471267 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 202773.189118 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 197964.839479 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 296650 # Transaction distribution
system.membus.trans_dist::ReadResp 296572 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 37110021 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 10437 # Total snoops (count)
-system.membus.snoop_fanout::samples 594010 # Request fanout histogram
+system.membus.snoop_fanout::samples 614132 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 594010 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 614132 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 594010 # Request fanout histogram
+system.membus.snoop_fanout::total 614132 # Request fanout histogram
system.membus.reqLayer0.occupancy 36342500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1279237311 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 10962579 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 213083141 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 72565 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3405571 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.012264 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.110061 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3425693 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.012192 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.109741 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3363806 98.77% 98.77% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 41765 1.23% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3383928 98.78% 98.78% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 41765 1.22% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3405571 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3425693 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2521355915 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 243000 # Layer occupancy (ticks)
sim_ticks 1861005569500 # Number of ticks simulated
final_tick 1861005569500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 145313 # Simulator instruction rate (inst/s)
-host_op_rate 145313 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5108711594 # Simulator tick rate (ticks/s)
-host_mem_usage 309496 # Number of bytes of host memory used
-host_seconds 364.28 # Real time elapsed on the host
+host_inst_rate 152837 # Simulator instruction rate (inst/s)
+host_op_rate 152837 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5373256396 # Simulator tick rate (ticks/s)
+host_mem_usage 376300 # Number of bytes of host memory used
+host_seconds 346.35 # Real time elapsed on the host
sim_insts 52934565 # Number of instructions simulated
sim_ops 52934565 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesWrittenSys 10176576 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 99 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 25870 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 187 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 189 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 25748 # Per bank write bursts
system.physmem.perBankRdBursts::1 25559 # Per bank write bursts
system.physmem.perBankRdBursts::2 25508 # Per bank write bursts
system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4847 # Writes before turning the bus around for reads
-system.physmem.totQLat 3741903500 # Total ticks spent queuing
-system.physmem.totMemAccLat 11312066000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 3741904500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11312067000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2018710000 # Total ticks spent in databus transfers
system.physmem.avgQLat 9268.06 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.cpu.decode.SquashedInsts 134238 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 584855 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 24961940 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 51456366 # Number of cycles rename is blocking
+system.cpu.rename.BlockCycles 51456440 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 20841952 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 10391329 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 8777565 # Number of cycles rename is unblocking
+system.cpu.rename.RunCycles 10391328 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 8777492 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 65857652 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 204161 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2078785 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 153522 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 4578544 # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents 4578470 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 43917673 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 79850033 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 79669145 # Number of integer rename lookups
system.cpu.rename.UndoneMaps 5775237 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1690640 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 240974 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13460569 # count of insts added to the skid buffer
+system.cpu.rename.skidInsts 13460579 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 10430513 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 6961741 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1496363 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 1107330 # Number of conflicting stores.
+system.cpu.memDep0.conflictingStores 1107333 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 58622970 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2136022 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 57539781 # Number of instructions issued
system.cpu.iq.issued_per_cycle::mean 0.491734 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.229968 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 93391036 79.81% 79.81% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 10179391 8.70% 88.51% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 93391037 79.81% 79.81% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 10179390 8.70% 88.51% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 4310458 3.68% 92.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 3008330 2.57% 94.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 3008329 2.57% 94.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 3082993 2.63% 97.40% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 1515378 1.30% 98.70% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1001152 0.86% 99.55% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 1515380 1.30% 98.70% # Number of insts issued each cycle
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system.cpu.iq.issued_per_cycle::7 403458 0.34% 99.90% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 121813 0.10% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.84% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.84% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 537781 48.22% 67.06% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 367353 32.94% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 367354 32.94% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 7286 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 57539781 # Type of FU issued
system.cpu.iq.rate 0.469435 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1115222 # FU busy when requested
+system.cpu.iq.fu_busy_cnt 1115223 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.019382 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 232558247 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 232558248 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 68266797 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 55883323 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 713260 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 336497 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 329169 # Number of floating instruction queue wakeup accesses
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+system.cpu.iq.int_alu_accesses 58264569 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 383149 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 636979 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 18243 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 442852 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.cacheBlocked 442853 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 584855 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 48003305 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 1105801 # Number of cycles IEW is unblocking
+system.cpu.iew.iewUnblockCycles 1105875 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 64465821 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 144286 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 10430513 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 6961741 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1886655 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 45598 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 856378 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 856452 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 20302 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 189944 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 410798 # Number of branches that were predicted not taken incorrectly
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 95814381 82.90% 82.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 7848857 6.79% 89.69% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::3 2211253 1.91% 95.30% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::5 615369 0.53% 97.36% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::7 490996 0.42% 98.20% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.op_class_0::IprAccess 948942 1.69% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 56123349 # Class of committed instruction
-system.cpu.commit.bw_lim_events 2085445 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 177593269 # The number of ROB reads
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+system.cpu.rob.rob_reads 177593268 # The number of ROB reads
system.cpu.rob.rob_writes 130137832 # The number of ROB writes
system.cpu.timesIdled 572499 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 5558352 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.dcache.overall_misses::total 3751566 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 41841354315 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 41841354315 # number of ReadReq miss cycles
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system.cpu.dcache.LoadLockedReq_miss_latency::total 376182249 # number of LoadLockedReq miss cycles
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system.cpu.dcache.StoreCondReq_miss_latency::total 455005 # number of StoreCondReq miss cycles
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23287.658005 # average ReadReq miss latency
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system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 16166.670205 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16852.037037 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16852.037037 # average StoreCondReq miss latency
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system.cpu.dcache.blocked_cycles::no_targets 2036 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 88.521739 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1032757 # number of replacements
system.cpu.icache.tags.tagsinuse 509.197301 # Cycle average of tags in use
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60628.026766 # average ReadReq mshr miss latency
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system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 17801 # average SCUpgradeReq mshr miss latency
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2143279 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2143168 # Transaction distribution
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system.cpu.toL2Bus.pkt_size::total 209949484 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 42097 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.occupancy 2495140999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1554402947 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
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system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.membus.trans_dist::Writeback 117457 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 185 # Transaction distribution
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system.membus.trans_dist::SCUpgradeReq 5 # Transaction distribution
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system.membus.trans_dist::ReadExReq 115137 # Transaction distribution
system.membus.trans_dist::ReadExResp 115137 # Transaction distribution
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system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124804 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 124804 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 44140 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30705344 # Cumulative packet size per connected master and slave (bytes)
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system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36066540 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 435 # Total snoops (count)
-system.membus.snoop_fanout::samples 563651 # Request fanout histogram
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 563651 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 563651 # Request fanout histogram
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system.membus.reqLayer0.occupancy 29181000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
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system.membus.reqLayer1.utilization 0.1 # Layer utilization (%)
system.membus.reqLayer2.occupancy 118000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2139454565 # Layer occupancy (ticks)
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system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 42497997 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
sim_ticks 1841538755500 # Number of ticks simulated
final_tick 1841538755500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 221247 # Simulator instruction rate (inst/s)
-host_op_rate 221247 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5777125497 # Simulator tick rate (ticks/s)
-host_mem_usage 308008 # Number of bytes of host memory used
-host_seconds 318.76 # Real time elapsed on the host
+host_inst_rate 221997 # Simulator instruction rate (inst/s)
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+host_mem_usage 374488 # Number of bytes of host memory used
+host_seconds 317.69 # Real time elapsed on the host
sim_insts 70525499 # Number of instructions simulated
sim_ops 70525499 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.overall_mshr_misses::cpu1.data 140963 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 365873 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 506836 # number of overall MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2114965000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 4270329509 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 6385294509 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 26925.029901 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19926.957037 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21873.285524 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 201881.578947 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 211980.806142 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207804.690432 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 212719.971056 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 209384.795870 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 210696.840307 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 207911.634461 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 210483.216026 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 209449.255422 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 964809 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.919385 # Cycle average of tags in use
system.l2c.overall_mshr_misses::cpu2.inst 4814 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 41256 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 81979 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 1102 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data 1563 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 2665 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 1382 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data 2131 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 3513 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 2484 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data 3694 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 6178 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 158665250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 968947500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 340372000 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70704.611550 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 70320.426823 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 67183.160187 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187881.578947 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 197980.806142 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 193804.690432 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 199719.971056 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196384.795870 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 197696.840307 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 194467.995169 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 197060.097455 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 196017.886047 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 295002 # Transaction distribution
system.membus.trans_dist::ReadResp 294996 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 5323648 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36001472 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 157 # Total snoops (count)
-system.membus.snoop_fanout::samples 562136 # Request fanout histogram
+system.membus.snoop_fanout::samples 579090 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 562136 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 579090 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 562136 # Request fanout histogram
+system.membus.snoop_fanout::total 579090 # Request fanout histogram
system.membus.reqLayer0.occupancy 11072500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 412860298 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 142733184 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 204523392 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 41934 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3236737 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012895 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.112822 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3253691 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012828 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.112532 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 3194999 98.71% 98.71% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 41738 1.29% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3211953 98.72% 98.72% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 41738 1.28% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3236737 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3253691 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1080719000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 82500 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 2.846097 # Number of seconds simulated
-sim_ticks 2846097440000 # Number of ticks simulated
-final_tick 2846097440000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.846145 # Number of seconds simulated
+sim_ticks 2846145040000 # Number of ticks simulated
+final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 101530 # Simulator instruction rate (inst/s)
-host_op_rate 122947 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2278332577 # Simulator tick rate (ticks/s)
-host_mem_usage 584920 # Number of bytes of host memory used
-host_seconds 1249.20 # Real time elapsed on the host
-sim_insts 126830911 # Number of instructions simulated
-sim_ops 153585651 # Number of ops (including micro ops) simulated
+host_inst_rate 162017 # Simulator instruction rate (inst/s)
+host_op_rate 196203 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3671761280 # Simulator tick rate (ticks/s)
+host_mem_usage 648900 # Number of bytes of host memory used
+host_seconds 775.14 # Real time elapsed on the host
+sim_insts 125586921 # Number of instructions simulated
+sim_ops 152085297 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 9344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1671232 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1335292 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8458880 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 1344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 217280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 606496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 432576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12733532 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1671232 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 217280 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1888512 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8840256 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
+system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8858000 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 146 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26113 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 21389 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 132170 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 21 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 3395 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 9500 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 6759 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 199510 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 138129 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 142565 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 3283 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 587201 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 469166 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2972098 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 472 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 76343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 213097 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 151989 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4474032 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 587201 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 76343 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 663544 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 3106097 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6220 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3112332 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 3106097 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 3283 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 587201 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 475386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2972098 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 472 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 76343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 213111 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 151989 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7586364 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 199510 # Number of read requests accepted
-system.physmem.writeReqs 178789 # Number of write requests accepted
-system.physmem.readBursts 199510 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 178789 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12761024 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9911424 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 12733532 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 11176336 # Total written bytes from the system interface side
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 2846096933500 # Total gap between requests
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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-system.physmem.bytesPerActivate::mean 249.927069 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 140.222601 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 310.362875 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 47359 52.21% 52.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 17889 19.72% 71.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6289 6.93% 78.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3581 3.95% 82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2839 3.13% 85.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1568 1.73% 87.66% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::1024-1151 9187 10.13% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 90716 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6524 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 30.562538 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 556.578248 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6523 99.98% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 23.737891 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::160-175 5 0.08% 98.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 20 0.31% 98.70% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::256-271 3 0.05% 99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 2 0.03% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 5 0.08% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 4 0.06% 99.49% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 4 0.06% 99.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 14 0.21% 99.77% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 2 0.03% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479 1 0.02% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 2 0.03% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 2 0.03% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 3 0.05% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591 1 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::720-735 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6524 # Writes before turning the bus around for reads
-system.physmem.totQLat 5679096455 # Total ticks spent queuing
-system.physmem.totMemAccLat 9417677705 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 996955000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 28482.21 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 11 0.17% 98.42% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 6 0.09% 98.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 17 0.26% 98.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 19 0.29% 99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 5 0.08% 99.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 3 0.05% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 2 0.03% 99.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 1 0.02% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.03% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 3 0.05% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads
+system.physmem.totQLat 5766362365 # Total ticks spent queuing
+system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 47232.21 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.48 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
-system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
+system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.18 # Average write queue length when enqueuing
-system.physmem.readRowHits 166067 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97473 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.93 # Row buffer hit rate for writes
-system.physmem.avgGap 7523405.91 # Average gap between requests
-system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 359115120 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 195945750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 815841000 # Energy for read commands per rank (pJ)
+system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing
+system.physmem.readRowHits 165729 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97368 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes
+system.physmem.avgGap 7522298.90 # Average gap between requests
+system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83249453610 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1634629745250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1905658854330 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.570214 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2719227401175 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95037280000 # Time in different power states
+system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.569329 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31827968825 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 326697840 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 178257750 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 739401000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 487697760 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 185892919680 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82096607520 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1635641013750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1905362595300 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.466120 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2720918284391 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95037280000 # Time in different power states
+system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.475203 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30141762609 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 20630955 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 13593557 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1040069 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 13124579 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 9315197 # Number of BTB hits
+system.cpu0.branchPred.lookups 33812647 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 70.975206 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 3367508 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 204886 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 69457 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 69457 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46535 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22922 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 69457 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 69457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 69457 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6849 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 9469.922616 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 8283.824538 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 6457.338241 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 6642 96.98% 96.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 191 2.79% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.10% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6849 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 65253 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5259 76.78% 76.78% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1590 23.22% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6849 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69457 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69457 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6849 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6849 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 76306 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 17312533 # DTB read hits
-system.cpu0.dtb.read_misses 63301 # DTB read misses
-system.cpu0.dtb.write_hits 14536158 # DTB write hits
-system.cpu0.dtb.write_misses 6156 # DTB write misses
+system.cpu0.dtb.read_hits 22995822 # DTB read hits
+system.cpu0.dtb.read_misses 59685 # DTB read misses
+system.cpu0.dtb.write_hits 17147924 # DTB write hits
+system.cpu0.dtb.write_misses 5568 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3522 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1254 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1942 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 17375834 # DTB read accesses
-system.cpu0.dtb.write_accesses 14542314 # DTB write accesses
+system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 23055507 # DTB read accesses
+system.cpu0.dtb.write_accesses 17153492 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 31848691 # DTB hits
-system.cpu0.dtb.misses 69457 # DTB misses
-system.cpu0.dtb.accesses 31918148 # DTB accesses
+system.cpu0.dtb.hits 40143746 # DTB hits
+system.cpu0.dtb.misses 65253 # DTB misses
+system.cpu0.dtb.accesses 40208999 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 3833 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2419 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 9485.117817 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 8378.584027 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 4911.792845 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 918 37.95% 37.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1466 60.60% 98.55% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 5 0.21% 98.76% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 29 1.20% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 3866 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2419 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2119 87.60% 87.60% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 300 12.40% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2419 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2419 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2419 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 6252 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 38694088 # ITB inst hits
-system.cpu0.itb.inst_misses 3833 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 68390761 # ITB inst hits
+system.cpu0.itb.inst_misses 3866 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2222 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 7309 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 38697921 # ITB inst accesses
-system.cpu0.itb.hits 38694088 # DTB hits
-system.cpu0.itb.misses 3833 # DTB misses
-system.cpu0.itb.accesses 38697921 # DTB accesses
-system.cpu0.numCycles 164664294 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses
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+system.cpu0.itb.accesses 68394627 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 79545676 # Number of instructions committed
-system.cpu0.committedOps 95726645 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 5037895 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 1845 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5527555817 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.070060 # CPI: cycles per instruction
-system.cpu0.ipc 0.483078 # IPC: instructions per cycle
+system.cpu0.committedInsts 104715622 # Number of instructions committed
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+system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.153342 # CPI: cycles per instruction
+system.cpu0.ipc 0.464394 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1847 # number of quiesce instructions executed
-system.cpu0.tickCycles 127989646 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 36674648 # Total number of cycles that the object has spent stopped
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-system.cpu0.dcache.tags.tagsinuse 500.482804 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 30358451 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 714416 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 42.494080 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 348749500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.482804 # Average occupied blocks per requestor
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-system.cpu0.dcache.tags.occ_percent::total 0.977505 # Average percentage of cache occupancy
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+system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use
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+system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit.
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 66 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
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system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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-system.cpu0.dcache.tags.data_accesses 63703980 # Number of data accesses
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-system.cpu0.dcache.ReadReq_hits::total 15781686 # number of ReadReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total 321521 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365596 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 365596 # number of LoadLockedReq hits
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-system.cpu0.dcache.overall_hits::total 29521406 # number of overall hits
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-system.cpu0.dcache.ReadReq_misses::total 463568 # number of ReadReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total 136519 # number of SoftPFReq misses
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-system.cpu0.dcache.LoadLockedReq_misses::total 21073 # number of LoadLockedReq misses
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-system.cpu0.dcache.StoreCondReq_misses::total 20283 # number of StoreCondReq misses
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-system.cpu0.dcache.overall_miss_rate::total 0.038353 # miss rate for overall accesses
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-system.cpu0.dcache.ReadReq_avg_miss_latency::total 13233.962530 # average ReadReq miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22376.288912 # average StoreCondReq miss latency
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+system.cpu0.dcache.overall_accesses::cpu0.data 39005896 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 39005896 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020110 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.020110 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033415 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.033415 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300291 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300291 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055072 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055072 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056988 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056988 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025843 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.025843 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028934 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.028934 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15387.148868 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14675.361826 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 14675.361826 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12973.755893 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12973.755893 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 513522 # number of writebacks
-system.cpu0.dcache.writebacks::total 513522 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72271 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 72271 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253439 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 253439 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14656 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14656 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 325710 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 325710 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 325710 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 325710 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391297 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 391297 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323871 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 323871 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103394 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 103394 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6417 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6417 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20283 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20283 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 715168 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 715168 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 818562 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 818562 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4428376943 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4428376943 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4906976685 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4906976685 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1616801678 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1616801678 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 95832009 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 95832009 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 422721232 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 422721232 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 436500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 436500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335353628 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9335353628 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10952155306 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10952155306 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276481750 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276481750 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3261665000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3261665000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7538146750 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7538146750 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024087 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024087 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023141 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023141 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225731 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225731 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016596 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053129 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053129 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023649 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.023649 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026664 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.026664 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11317.175810 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11317.175810 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15151.022120 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15151.022120 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15637.287251 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15637.287251 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14934.082749 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14934.082749 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20841.159197 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20841.159197 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 490183 # number of writebacks
+system.cpu0.dcache.writebacks::total 490183 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 69583 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 69583 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 243174 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 243174 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14803 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14803 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 312757 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 312757 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 312757 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 312757 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 371857 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 371857 # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total 312047 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99536 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 99536 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6041 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6041 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 683904 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 683904 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 783440 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 783440 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29433 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29433 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26165 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26165 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55598 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55598 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4208861714 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4208861714 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 579500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10569422511 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 10569422511 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9888636999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018780 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226570 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056988 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13053.371555 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13053.371555 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13379.750472 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13379.750472 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1969157 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.783924 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 36716761 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1969669 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 18.641082 # Average number of references to valid blocks.
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+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 282144500 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5673424250 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4065113000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 282144500 # number of overall MSHR uncacheable cycles
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+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.211100 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067656 # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482875 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482875 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.909378 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.909378 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.498538 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.498538 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915650 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915650 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157671 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157671 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075961 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010905 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.026439 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036152 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.185051 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158018 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158018 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.076207 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010033 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.027480 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.033826 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163120 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23400.009493 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30053.081217 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58459.199979 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20172.381963 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20172.381963 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14669.747940 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14669.747940 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 345999 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 345999 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38178.292804 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38178.292804 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31655.164692 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28958.239910 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16654.867257 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39438.365502 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27791.679436 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58459.199979 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45977.272768 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162550 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 466499 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 466499 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503 # average overall mshr miss latency
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency
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+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 2703667 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2643606 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 19130 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 19130 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 513519 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 304285 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 88848 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42983 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 113085 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 297594 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 284124 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3946133 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2385460 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11633 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174179 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6517405 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126276224 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86385120 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17096 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 213005640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 651207 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3963380 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.135029 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.341755 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 661406 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 3428208 86.50% 86.50% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 535172 13.50% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3963380 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 2258643996 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 116241999 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 2965047043 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1230256203 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 7364491 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 92392742 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 18842889 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 6205402 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 629106 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 9920552 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 7177439 # Number of BTB hits
+system.cpu1.branchPred.lookups 5430284 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.349190 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 8245946 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 413041 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 26188 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 26188 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19132 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7056 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 26188 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 26188 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 26188 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2719 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 9780.159618 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 8826.212048 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 5631.617808 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 919 33.80% 33.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1662 61.13% 94.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 68 2.50% 97.43% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 62 2.28% 99.71% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 3 0.11% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2719 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1631340764 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1631340764 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1631340764 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 2011 73.96% 73.96% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 708 26.04% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2719 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26188 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 30040 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26188 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2719 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2719 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 28907 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 11112548 # DTB read hits
-system.cpu1.dtb.read_misses 24192 # DTB read misses
-system.cpu1.dtb.write_hits 6961122 # DTB write hits
-system.cpu1.dtb.write_misses 1996 # DTB write misses
+system.cpu1.dtb.read_hits 5155380 # DTB read hits
+system.cpu1.dtb.read_misses 27847 # DTB read misses
+system.cpu1.dtb.write_hits 4232538 # DTB write hits
+system.cpu1.dtb.write_misses 2193 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2061 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 148 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 422 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 278 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 11136740 # DTB read accesses
-system.cpu1.dtb.write_accesses 6963118 # DTB write accesses
+system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 5183227 # DTB read accesses
+system.cpu1.dtb.write_accesses 4234731 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 18073670 # DTB hits
-system.cpu1.dtb.misses 26188 # DTB misses
-system.cpu1.dtb.accesses 18099858 # DTB accesses
+system.cpu1.dtb.hits 9387918 # DTB hits
+system.cpu1.dtb.misses 30040 # DTB misses
+system.cpu1.dtb.accesses 9417958 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 2252 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 2252 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2071 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 2252 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 2252 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 2252 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 9763.181412 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 8935.720507 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 4528.605471 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095 139 12.42% 12.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 170 15.19% 27.61% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 525 46.92% 74.53% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 97.14% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.32% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 21 1.88% 99.20% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 7 0.63% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1630766264 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1630766264 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1630766264 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 2268 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2252 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2252 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 3371 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 39781680 # ITB inst hits
-system.cpu1.itb.inst_misses 2252 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 10199097 # ITB inst hits
+system.cpu1.itb.inst_misses 2268 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1899 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 39783932 # ITB inst accesses
-system.cpu1.itb.hits 39781680 # DTB hits
-system.cpu1.itb.misses 2252 # DTB misses
-system.cpu1.itb.accesses 39783932 # DTB accesses
-system.cpu1.numCycles 114623988 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses
+system.cpu1.itb.hits 10199097 # DTB hits
+system.cpu1.itb.misses 2268 # DTB misses
+system.cpu1.itb.accesses 10201365 # DTB accesses
+system.cpu1.numCycles 54377537 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 47285235 # Number of instructions committed
-system.cpu1.committedOps 57859006 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 5005620 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 2776 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5576963738 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.424097 # CPI: cycles per instruction
-system.cpu1.ipc 0.412525 # IPC: instructions per cycle
+system.cpu1.committedInsts 20871299 # Number of instructions committed
+system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.605374 # CPI: cycles per instruction
+system.cpu1.ipc 0.383822 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2776 # number of quiesce instructions executed
-system.cpu1.tickCycles 97884766 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 16739222 # Total number of cycles that the object has spent stopped
-system.cpu1.dcache.tags.replacements 194739 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 472.948438 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 17633406 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 195100 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 90.381374 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 90504077500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.948438 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.923727 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.923727 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 361 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 306 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 55 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.705078 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 36178407 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 36178407 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 10725883 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 10725883 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 6668052 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 6668052 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49984 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 49984 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80051 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 80051 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71499 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 71499 # number of StoreCondReq hits
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-system.cpu1.dcache.ReadReq_misses::total 157968 # number of ReadReq misses
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-system.cpu1.dcache.SoftPFReq_misses::total 30816 # number of SoftPFReq misses
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-system.cpu1.dcache.LoadLockedReq_misses::total 16919 # number of LoadLockedReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 23678 # number of StoreCondReq misses
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-system.cpu1.dcache.overall_misses::total 333510 # number of overall misses
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-system.cpu1.dcache.ReadReq_miss_latency::total 2315952429 # number of ReadReq miss cycles
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-system.cpu1.dcache.LoadLockedReq_miss_latency::total 316030492 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 124000 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96970 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174477 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14660.896061 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14660.896061 # average ReadReq miss latency
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-system.cpu1.dcache.WriteReq_avg_miss_latency::total 26680.667772 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18679.029021 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18679.029021 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23526.571290 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23526.571290 # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed
+system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked
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+system.cpu1.dcache.tags.replacements 231595 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 482.666397 # Cycle average of tags in use
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+system.cpu1.dcache.tags.avg_refs 38.362674 # Average number of references to valid blocks.
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+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14593.002793 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14593.002793 # average ReadReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20407.866535 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 20407.866535 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18522.199493 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18522.199493 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 17745.850925 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 119475 # number of writebacks
-system.cpu1.dcache.writebacks::total 119475 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 16075 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 16075 # number of ReadReq MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 68340 # number of overall MSHR hits
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-system.cpu1.dcache.overall_mshr_misses::total 264289 # number of overall MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 79878753 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency::total 4171635396 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322015751 # number of ReadReq MSHR uncacheable cycles
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-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843986000 # number of WriteReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166001751 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013037 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013037 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013572 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013572 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.370483 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.370483 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050366 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050366 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248779 # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::total 0.013243 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014867 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.014867 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13189.224155 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13189.224155 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24877.265150 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24877.265150 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16277.459863 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16277.459863 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16355.191032 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16355.191032 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21970.071163 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21970.071163 # average StoreCondReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12272 # number of LoadLockedReq MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5441 # number of LoadLockedReq MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5716 # number of ReadReq MSHR uncacheable
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+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025986 # mshr miss rate for WriteReq accesses
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051407 # mshr miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226809 # mshr miss rate for StoreCondReq accesses
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency
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+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988 # average WriteReq mshr miss latency
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17800.572621 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17800.572621 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17628.055488 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17628.055488 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 947666 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.322678 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 38831450 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 948178 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 40.953756 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 72138919500 # Cycle when the warmup percentage was hit.
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-system.cpu1.icache.tags.occ_percent::total 0.975240 # Average percentage of cache occupancy
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+system.cpu1.icache.tags.warmup_cycle 72123856500 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id
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-system.cpu1.icache.ReadReq_hits::total 38831450 # number of ReadReq hits
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-system.cpu1.icache.ReadReq_misses::total 948178 # number of ReadReq misses
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-system.cpu1.icache.demand_miss_latency::total 8186316171 # number of demand (read+write) miss cycles
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 8633.733509 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 8633.733509 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8633.733509 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8633.733509 # average overall miss latency
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+system.cpu1.icache.overall_miss_rate::total 0.101926 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8872.874508 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8872.874508 # average ReadReq miss latency
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+system.cpu1.icache.demand_avg_miss_latency::total 8872.874508 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8872.874508 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 948178 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 948178 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_misses::total 948178 # number of demand (read+write) MSHR misses
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-system.cpu1.icache.overall_mshr_misses::total 948178 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 7236829829 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10429000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10429000 # number of overall MSHR uncacheable cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 7632.353660 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7632.353660 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 92232.142857 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.l2cache.prefetcher.pfIdentified 198250 # number of prefetch candidates identified
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.093163 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4379.239024 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2180.842140 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 842.800943 # Average occupied blocks per requestor
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-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 384 # Occupied blocks per task id
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-system.cpu1.l2cache.Writeback_accesses::total 119475 # number of Writeback accesses(hits+misses)
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-system.cpu1.l2cache.UpgradeReq_accesses::total 29921 # number of UpgradeReq accesses(hits+misses)
-system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23677 # number of SCUpgradeReq accesses(hits+misses)
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+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1546268 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1215347 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 11936 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 119475 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 29668 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 76508 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42110 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 86467 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 85086 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 67037 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1896584 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 833808 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7155 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62301 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2799848 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60690688 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25792980 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 116228 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 86611224 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 603822 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1920664 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.272089 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.445035 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 669363 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 1398073 72.79% 72.79% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 522591 27.21% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1920664 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 837814982 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 80458500 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1423116171 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 410915491 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 4323500 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 33252737 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31003 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31003 # Transaction distribution
+system.iobus.trans_dist::ReadReq 30987 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30987 # Transaction distribution
system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
system.iobus.trans_dist::WriteResp 23198 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72906 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72906 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180818 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321064 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2483858 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 198973953 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 198858516 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36786758 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 36733518 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 36449 # number of replacements
-system.iocache.tags.tagsinuse 14.479940 # Cycle average of tags in use
+system.iocache.tags.replacements 36403 # number of replacements
+system.iocache.tags.tagsinuse 1.010559 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 36419 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 270378265000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.479940 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.904996 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.904996 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 270375766000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.010559 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.063160 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.063160 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328203 # Number of tag accesses
-system.iocache.tags.data_accesses 328203 # Number of data accesses
-system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
+system.iocache.tags.tag_accesses 328077 # Number of tag accesses
+system.iocache.tags.data_accesses 328077 # Number of data accesses
+system.iocache.ReadReq_misses::realview.ide 229 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 229 # number of ReadReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses
-system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
-system.iocache.demand_misses::total 243 # number of demand (read+write) misses
-system.iocache.overall_misses::realview.ide 243 # number of overall misses
-system.iocache.overall_misses::total 243 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31380127 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31380127 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6638963068 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 6638963068 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31380127 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31380127 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31380127 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31380127 # number of overall miss cycles
-system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::realview.ide 229 # number of demand (read+write) misses
+system.iocache.demand_misses::total 229 # number of demand (read+write) misses
+system.iocache.overall_misses::realview.ide 229 # number of overall misses
+system.iocache.overall_misses::total 229 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 29476377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 29476377 # number of ReadReq miss cycles
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+system.l2c.overall_mshr_uncacheable_latency::total 10146918501 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.154815 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.172068 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.497459 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.748777 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.813546 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.768440 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764205 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.931486 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.856476 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.731888 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.792373 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.756909 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.515074 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.257426 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.013514 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.314400 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.277480 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.739466 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.193237 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035714 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.217835 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.448603 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.530662 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.515074 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75854.403149 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90812.054018 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 79090.867580 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122229.036396 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 87801.166169 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17751.429622 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17758.884431 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17753.216423 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17896.675112 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.948923 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.447505 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79077.135895 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69691.543041 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 75064.022094 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78696.917808 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75518.687414 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77572.373631 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::total 88252.612732 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17835.761921 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17962.271539 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17876.422915 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17880.799257 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17771.656198 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17815.324244 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80402.981575 # average ReadExReq mshr miss latency
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system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency
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system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68207.465922 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77572.664185 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76892.857143 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70560.885515 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70775.623552 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::total 86523.829726 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 214962 # Transaction distribution
-system.membus.trans_dist::ReadResp 214962 # Transaction distribution
-system.membus.trans_dist::WriteReq 31066 # Transaction distribution
-system.membus.trans_dist::WriteResp 31066 # Transaction distribution
-system.membus.trans_dist::Writeback 138129 # Transaction distribution
+system.membus.trans_dist::ReadReq 215059 # Transaction distribution
+system.membus.trans_dist::ReadResp 215059 # Transaction distribution
+system.membus.trans_dist::WriteReq 31175 # Transaction distribution
+system.membus.trans_dist::WriteResp 31175 # Transaction distribution
+system.membus.trans_dist::Writeback 138467 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 76255 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40796 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 14193 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution
-system.membus.trans_dist::ReadExReq 40018 # Transaction distribution
-system.membus.trans_dist::ReadExResp 19540 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
+system.membus.trans_dist::ReadExReq 39963 # Transaction distribution
+system.membus.trans_dist::ReadExResp 19392 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661851 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 783963 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108912 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 108912 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 892875 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19273388 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19465716 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 24102196 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 123912 # Total snoops (count)
-system.membus.snoop_fanout::samples 507941 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 126068 # Total snoops (count)
+system.membus.snoop_fanout::samples 580884 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 507941 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 507941 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88612000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 580884 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12528499 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1167691410 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1172073016 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37476242 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 516720 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 516705 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31066 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31066 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 232835 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36251 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 79932 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41134 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 121066 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 51762 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 51762 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083099 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338756 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1421855 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34093856 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5618324 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 39712180 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 288702 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 920160 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.039660 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.195160 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 293844 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 883666 96.03% 96.03% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36494 3.97% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 920160 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 787000770 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 681574777 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 259216519 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.852832 # Number of seconds simulated
-sim_ticks 2852831758500 # Number of ticks simulated
-final_tick 2852831758500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.852840 # Number of seconds simulated
+sim_ticks 2852839554500 # Number of ticks simulated
+final_tick 2852839554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 111123 # Simulator instruction rate (inst/s)
-host_op_rate 134357 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2834419538 # Simulator tick rate (ticks/s)
-host_mem_usage 554504 # Number of bytes of host memory used
-host_seconds 1006.50 # Real time elapsed on the host
-sim_insts 111845135 # Number of instructions simulated
-sim_ops 135229426 # Number of ops (including micro ops) simulated
+host_inst_rate 169032 # Simulator instruction rate (inst/s)
+host_op_rate 204382 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4294589830 # Simulator tick rate (ticks/s)
+host_mem_usage 620820 # Number of bytes of host memory used
+host_seconds 664.29 # Real time elapsed on the host
+sim_insts 112285680 # Number of instructions simulated
+sim_ops 135768245 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.dtb.walker 7744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1669888 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9170532 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 7680 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 1672128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9190636 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10849188 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1669888 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1669888 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7971008 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10871532 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1672128 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1672128 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7983360 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7988532 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.dtb.walker 121 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 26092 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 143809 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8000884 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 120 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 26127 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 144125 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 170038 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 124547 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170389 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 124740 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 128928 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.dtb.walker 2714 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 585344 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3214537 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 129121 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 2692 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 586128 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3221575 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3802954 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 585344 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 585344 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2794069 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3810776 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 586128 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 586128 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2798391 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2800211 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2794069 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 2714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 585344 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3220679 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2804533 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2798391 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 2692 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 586128 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3227717 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6603165 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 170038 # Number of read requests accepted
-system.physmem.writeReqs 165152 # Number of write requests accepted
-system.physmem.readBursts 170038 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 165152 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10876672 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 5760 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9051328 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10849188 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10306868 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 90 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 23701 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4591 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10711 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10418 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10743 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10617 # Per bank write bursts
-system.physmem.perBankRdBursts::4 13557 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10851 # Per bank write bursts
-system.physmem.perBankRdBursts::6 10986 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10951 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10335 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10516 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10068 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9192 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10325 # Per bank write bursts
-system.physmem.perBankRdBursts::13 10893 # Per bank write bursts
-system.physmem.perBankRdBursts::14 9864 # Per bank write bursts
-system.physmem.perBankRdBursts::15 9921 # Per bank write bursts
-system.physmem.perBankWrBursts::0 8907 # Per bank write bursts
-system.physmem.perBankWrBursts::1 8809 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9307 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9147 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8787 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9076 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9209 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9123 # Per bank write bursts
-system.physmem.perBankWrBursts::8 9054 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9064 # Per bank write bursts
-system.physmem.perBankWrBursts::10 8553 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8266 # Per bank write bursts
-system.physmem.perBankWrBursts::12 8846 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9045 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8063 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8171 # Per bank write bursts
+system.physmem.bw_total::total 6615309 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170389 # Number of read requests accepted
+system.physmem.writeReqs 165345 # Number of write requests accepted
+system.physmem.readBursts 170389 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 165345 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10897024 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7872 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9054784 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10871532 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 10319220 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 123 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 23835 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 4587 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10917 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10861 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10721 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10725 # Per bank write bursts
+system.physmem.perBankRdBursts::4 13339 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10813 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11142 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10985 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10153 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10280 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10274 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9203 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10314 # Per bank write bursts
+system.physmem.perBankRdBursts::13 10760 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10035 # Per bank write bursts
+system.physmem.perBankRdBursts::15 9744 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9017 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9225 # Per bank write bursts
+system.physmem.perBankWrBursts::2 9344 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9210 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8591 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8923 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9235 # Per bank write bursts
+system.physmem.perBankWrBursts::7 9154 # Per bank write bursts
+system.physmem.perBankWrBursts::8 8919 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8830 # Per bank write bursts
+system.physmem.perBankWrBursts::10 8770 # Per bank write bursts
+system.physmem.perBankWrBursts::11 8263 # Per bank write bursts
+system.physmem.perBankWrBursts::12 8824 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8884 # Per bank write bursts
+system.physmem.perBankWrBursts::14 8238 # Per bank write bursts
+system.physmem.perBankWrBursts::15 8054 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 51 # Number of times write queue was full causing retry
-system.physmem.totGap 2852831352500 # Total gap between requests
+system.physmem.numWrRetry 37 # Number of times write queue was full causing retry
+system.physmem.totGap 2852839149500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 541 # Read request sizes (log2)
+system.physmem.readPktSize::2 543 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 169483 # Read request sizes (log2)
+system.physmem.readPktSize::6 169832 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 160771 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 163196 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 6460 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 160964 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 163637 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 6336 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 280 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1486 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1656 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5410 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 5965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 6172 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 7573 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 6474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 6716 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8051 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 6751 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 6513 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 8515 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 7300 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 6993 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6732 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::58 140 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63 157 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 61712 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 322.918330 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 189.336942 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 338.461853 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22238 36.04% 36.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14509 23.51% 59.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6552 10.62% 70.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3615 5.86% 76.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2651 4.30% 80.32% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1538 2.49% 82.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1136 1.84% 84.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1152 1.87% 86.52% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8321 13.48% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 61712 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5883 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.886962 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 584.019916 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5882 99.98% 99.98% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::63 43 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 61975 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 321.932134 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 188.780856 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 337.844354 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 22404 36.15% 36.15% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14558 23.49% 59.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6628 10.69% 70.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3590 5.79% 76.13% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2633 4.25% 80.38% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1568 2.53% 82.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1136 1.83% 84.74% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1187 1.92% 86.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8271 13.35% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 61975 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 5903 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.841945 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 583.033382 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 5902 99.98% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5883 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5883 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 24.039946 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.374321 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 43.145306 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 5549 94.32% 94.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 83 1.41% 95.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 21 0.36% 96.09% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 19 0.32% 96.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 30 0.51% 96.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 24 0.41% 97.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 22 0.37% 97.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 15 0.25% 97.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 11 0.19% 98.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 3 0.05% 98.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 21 0.36% 98.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 13 0.22% 98.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 9 0.15% 98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.03% 99.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 2 0.03% 99.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 4 0.07% 99.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 7 0.12% 99.29% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 3 0.05% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 2 0.03% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 6 0.10% 99.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 9 0.15% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 2 0.03% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 3 0.05% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479 2 0.03% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 2 0.03% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 1 0.02% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 5 0.08% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 2 0.03% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 5 0.08% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5883 # Writes before turning the bus around for reads
-system.physmem.totQLat 1723441444 # Total ticks spent queuing
-system.physmem.totMemAccLat 4909966444 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 849740000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10140.99 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 5903 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 5903 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.967644 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.368451 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 42.492651 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 5572 94.39% 94.39% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::48-63 22 0.37% 96.22% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::80-95 26 0.44% 96.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 23 0.39% 97.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 23 0.39% 97.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 20 0.34% 98.00% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::160-175 2 0.03% 98.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 23 0.39% 98.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 13 0.22% 98.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 11 0.19% 98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 2 0.03% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 2 0.03% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 3 0.05% 99.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 2 0.03% 99.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 6 0.10% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 7 0.12% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 5 0.08% 99.41% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::352-367 15 0.25% 99.70% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::416-431 1 0.02% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 3 0.05% 99.83% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::512-527 1 0.02% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.03% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 2 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::560-575 2 0.03% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::720-735 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 5903 # Writes before turning the bus around for reads
+system.physmem.totQLat 1723482630 # Total ticks spent queuing
+system.physmem.totMemAccLat 4915970130 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 851330000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10122.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28890.99 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 28872.29 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 3.82 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.17 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 3.81 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.62 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.05 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.38 # Average write queue length when enqueuing
-system.physmem.readRowHits 140236 # Number of row buffer hits during reads
-system.physmem.writeRowHits 109426 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 77.36 # Row buffer hit rate for writes
-system.physmem.avgGap 8511087.30 # Average gap between requests
-system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 243129600 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 132660000 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 692905200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 468925200 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83554754445 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1638403001250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1909828199775 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.450935 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2725489926444 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95262180000 # Time in different power states
+system.physmem.avgWrQLen 25.62 # Average write queue length when enqueuing
+system.physmem.readRowHits 140451 # Number of row buffer hits during reads
+system.physmem.writeRowHits 109320 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.49 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 77.25 # Row buffer hit rate for writes
+system.physmem.avgGap 8497319.75 # Average gap between requests
+system.physmem.pageHitRate 80.11 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 245019600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 133691250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 698123400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 471089520 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 83679210810 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1638298500750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1909858967970 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.459893 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2725317218918 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95262440000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 32075649806 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32255883582 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 223413120 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 121902000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 632681400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 447521760 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 186332824080 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82328316795 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1639478823750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1909565482905 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.358845 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2727297379194 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95262180000 # Time in different power states
+system.physmem_1.actEnergy 223511400 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 121955625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 629943600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 445707360 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 186333332640 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82264054140 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1639539866250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1909558371015 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.354525 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2727396126418 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95262440000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 30272102306 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30180892082 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 31016169 # Number of BP lookups
-system.cpu.branchPred.condPredicted 16821620 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2509164 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18454178 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13299317 # Number of BTB hits
+system.cpu.branchPred.lookups 31043514 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16869099 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2536489 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18574786 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13386311 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.066699 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7885459 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1501288 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 72.067108 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7804422 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1529182 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.dtb.walker.walks 66365 # Table walker walks requested
-system.cpu.dtb.walker.walksShort 66365 # Table walker walks initiated with short descriptors
-system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43579 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22786 # Level at which table walker walks with short descriptors terminate
-system.cpu.dtb.walker.walkWaitTime::samples 66365 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::0 66365 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkWaitTime::total 66365 # Table walker wait (enqueue to first request) latency
-system.cpu.dtb.walker.walkCompletionTime::samples 7796 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::mean 11013.949461 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::gmean 8730.002722 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::stdev 7624.437396 # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::0-16383 6093 78.16% 78.16% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::16384-32767 1696 21.75% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walks 65823 # Table walker walks requested
+system.cpu.dtb.walker.walksShort 65823 # Table walker walks initiated with short descriptors
+system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43117 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22706 # Level at which table walker walks with short descriptors terminate
+system.cpu.dtb.walker.walkWaitTime::samples 65823 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::0 65823 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkWaitTime::total 65823 # Table walker wait (enqueue to first request) latency
+system.cpu.dtb.walker.walkCompletionTime::samples 7829 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::mean 10980.553072 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::gmean 8717.816397 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::stdev 7451.711579 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::0-16383 6121 78.18% 78.18% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::16384-32767 1701 21.73% 99.91% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.05% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::229376-245759 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.dtb.walker.walkCompletionTime::total 7796 # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu.dtb.walker.walkCompletionTime::total 7829 # Table walker service (enqueue to completion) latency
system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution
system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution
-system.cpu.dtb.walker.walkPageSizes::4K 6406 82.17% 82.17% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::1M 1390 17.83% 100.00% # Table walker page sizes translated
-system.cpu.dtb.walker.walkPageSizes::total 7796 # Table walker page sizes translated
-system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66365 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkPageSizes::4K 6444 82.31% 82.31% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::1M 1385 17.69% 100.00% # Table walker page sizes translated
+system.cpu.dtb.walker.walkPageSizes::total 7829 # Table walker page sizes translated
+system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65823 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66365 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7796 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65823 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7829 # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7796 # Table walker requests started/completed, data/inst
-system.cpu.dtb.walker.walkRequestOrigin::total 74161 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7829 # Table walker requests started/completed, data/inst
+system.cpu.dtb.walker.walkRequestOrigin::total 73652 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24709745 # DTB read hits
-system.cpu.dtb.read_misses 59626 # DTB read misses
-system.cpu.dtb.write_hits 19412201 # DTB write hits
-system.cpu.dtb.write_misses 6739 # DTB write misses
+system.cpu.dtb.read_hits 24809902 # DTB read hits
+system.cpu.dtb.read_misses 58990 # DTB read misses
+system.cpu.dtb.write_hits 19469042 # DTB write hits
+system.cpu.dtb.write_misses 6833 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4351 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1292 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1782 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1238 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 733 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24769371 # DTB read accesses
-system.cpu.dtb.write_accesses 19418940 # DTB write accesses
+system.cpu.dtb.perms_faults 748 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24868892 # DTB read accesses
+system.cpu.dtb.write_accesses 19475875 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44121946 # DTB hits
-system.cpu.dtb.misses 66365 # DTB misses
-system.cpu.dtb.accesses 44188311 # DTB accesses
+system.cpu.dtb.hits 44278944 # DTB hits
+system.cpu.dtb.misses 65823 # DTB misses
+system.cpu.dtb.accesses 44344767 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.walker.walks 5448 # Table walker walks requested
-system.cpu.itb.walker.walksShort 5448 # Table walker walks initiated with short descriptors
-system.cpu.itb.walker.walksShortTerminationLevel::Level1 319 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walksShortTerminationLevel::Level2 5129 # Level at which table walker walks with short descriptors terminate
-system.cpu.itb.walker.walkWaitTime::samples 5448 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::0 5448 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkWaitTime::total 5448 # Table walker wait (enqueue to first request) latency
-system.cpu.itb.walker.walkCompletionTime::samples 3189 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::mean 11214.016933 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::gmean 8947.518192 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::stdev 7056.251032 # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::0-8191 1295 40.61% 40.61% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::8192-16383 1177 36.91% 77.52% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::16384-24575 716 22.45% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walks 5435 # Table walker walks requested
+system.cpu.itb.walker.walksShort 5435 # Table walker walks initiated with short descriptors
+system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walksShortTerminationLevel::Level2 5114 # Level at which table walker walks with short descriptors terminate
+system.cpu.itb.walker.walkWaitTime::samples 5435 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::0 5435 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkWaitTime::total 5435 # Table walker wait (enqueue to first request) latency
+system.cpu.itb.walker.walkCompletionTime::samples 3183 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::mean 11172.007540 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::gmean 8898.591631 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::stdev 7073.724538 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::0-8191 1308 41.09% 41.09% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::8192-16383 1159 36.41% 77.51% # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::16384-24575 715 22.46% 99.97% # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu.itb.walker.walkCompletionTime::total 3189 # Table walker service (enqueue to completion) latency
+system.cpu.itb.walker.walkCompletionTime::total 3183 # Table walker service (enqueue to completion) latency
system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution
system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution
-system.cpu.itb.walker.walkPageSizes::4K 2879 90.28% 90.28% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::1M 310 9.72% 100.00% # Table walker page sizes translated
-system.cpu.itb.walker.walkPageSizes::total 3189 # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::4K 2873 90.26% 90.26% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::1M 310 9.74% 100.00% # Table walker page sizes translated
+system.cpu.itb.walker.walkPageSizes::total 3183 # Table walker page sizes translated
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5448 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Requested::total 5448 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5435 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Requested::total 5435 # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3189 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin_Completed::total 3189 # Table walker requests started/completed, data/inst
-system.cpu.itb.walker.walkRequestOrigin::total 8637 # Table walker requests started/completed, data/inst
-system.cpu.itb.inst_hits 57588649 # ITB inst hits
-system.cpu.itb.inst_misses 5448 # ITB inst misses
+system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3183 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin_Completed::total 3183 # Table walker requests started/completed, data/inst
+system.cpu.itb.walker.walkRequestOrigin::total 8618 # Table walker requests started/completed, data/inst
+system.cpu.itb.inst_hits 57700454 # ITB inst hits
+system.cpu.itb.inst_misses 5435 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2978 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2972 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 8467 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 8445 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 57594097 # ITB inst accesses
-system.cpu.itb.hits 57588649 # DTB hits
-system.cpu.itb.misses 5448 # DTB misses
-system.cpu.itb.accesses 57594097 # DTB accesses
-system.cpu.numCycles 315565701 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 57705889 # ITB inst accesses
+system.cpu.itb.hits 57700454 # DTB hits
+system.cpu.itb.misses 5435 # DTB misses
+system.cpu.itb.accesses 57705889 # DTB accesses
+system.cpu.numCycles 315730000 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 111845135 # Number of instructions committed
-system.cpu.committedOps 135229426 # Number of ops (including micro ops) committed
-system.cpu.discardedOps 7692999 # Number of ops (including micro ops) which were discarded before commit
+system.cpu.committedInsts 112285680 # Number of instructions committed
+system.cpu.committedOps 135768245 # Number of ops (including micro ops) committed
+system.cpu.discardedOps 7761547 # Number of ops (including micro ops) which were discarded before commit
system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
-system.cpu.quiesceCycles 5390158471 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.cpi 2.821452 # CPI: cycles per instruction
-system.cpu.ipc 0.354427 # IPC: instructions per cycle
+system.cpu.quiesceCycles 5390009685 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.cpi 2.811846 # CPI: cycles per instruction
+system.cpu.ipc 0.355638 # IPC: instructions per cycle
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
-system.cpu.tickCycles 227544928 # Number of cycles that the object actually ticked
-system.cpu.idleCycles 88020773 # Total number of cycles that the object has spent stopped
-system.cpu.dcache.tags.replacements 842581 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.947861 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 42538360 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 843093 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 50.455122 # Average number of references to valid blocks.
+system.cpu.tickCycles 227805023 # Number of cycles that the object actually ticked
+system.cpu.idleCycles 87924977 # Total number of cycles that the object has spent stopped
+system.cpu.dcache.tags.replacements 842413 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.947858 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 42688411 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 842925 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 50.643190 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.947861 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.947858 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 351 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 54 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 175914832 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 175914832 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23018220 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23018220 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18257083 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18257083 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 356514 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 356514 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 443429 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 443429 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460179 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460179 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41275303 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41275303 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 41631817 # number of overall hits
-system.cpu.dcache.overall_hits::total 41631817 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 492255 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 492255 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 547766 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 547766 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 169911 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 169911 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22569 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22569 # number of LoadLockedReq misses
+system.cpu.dcache.tags.tag_accesses 176513094 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 176513094 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 23118388 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 23118388 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 18306742 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 18306742 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 356409 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 356409 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 443709 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 443709 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 460231 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 460231 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 41425130 # number of demand (read+write) hits
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-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17828.691754 # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 68500 # average SCUpgradeReq mshr miss latency
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+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150488.851829 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60444.435687 # average overall mshr uncacheable latency
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157452.139521 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 3579472 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3579378 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 698329 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2833 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 295899 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 295899 # Transaction distribution
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-system.cpu.toL2Bus.snoops 61238 # Total snoops (count)
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+system.cpu.toL2Bus.snoops 61425 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4542001 99.20% 99.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 36492 0.80% 100.00% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4578493 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 3014061750 # Layer occupancy (ticks)
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+system.cpu.toL2Bus.reqLayer0.occupancy 3012663750 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 211500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 4357263112 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1342100655 # Layer occupancy (ticks)
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system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 10577000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.occupancy 10549250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 89155750 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.occupancy 88533000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 30183 # Transaction distribution
system.iobus.trans_dist::ReadResp 30183 # Transaction distribution
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 198870981 # Layer occupancy (ticks)
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system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36810507 # Layer occupancy (ticks)
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system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36424 # number of replacements
-system.iocache.tags.tagsinuse 1.031296 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.031382 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 270543128000 # Cycle when the warmup percentage was hit.
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-system.iocache.tags.occ_percent::total 0.064456 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 270536492000 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 234 # number of overall misses
system.iocache.overall_misses::total 234 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 29239875 # number of ReadReq miss cycles
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system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
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-system.iocache.ReadReq_avg_miss_latency::total 124956.730769 # average ReadReq miss latency
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-system.iocache.WriteInvalidateReq_avg_miss_latency::total 183484.667596 # average WriteInvalidateReq miss latency
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-system.iocache.demand_avg_miss_latency::total 124956.730769 # average overall miss latency
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-system.iocache.overall_avg_miss_latency::total 124956.730769 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 22676 # number of cycles access was blocked
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+system.iocache.overall_avg_miss_latency::total 124939.645299 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 22431 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 3466 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 3441 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.542412 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.518745 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
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system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
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system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72337.081197 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 72337.081197 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131367.736114 # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131367.736114 # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 72337.081197 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 72337.081197 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 71736 # Transaction distribution
-system.membus.trans_dist::ReadResp 71736 # Transaction distribution
+system.membus.trans_dist::ReadReq 71805 # Transaction distribution
+system.membus.trans_dist::ReadResp 71805 # Transaction distribution
system.membus.trans_dist::WriteReq 27583 # Transaction distribution
system.membus.trans_dist::WriteResp 27583 # Transaction distribution
-system.membus.trans_dist::Writeback 124547 # Transaction distribution
+system.membus.trans_dist::Writeback 124740 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4587 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129383 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129383 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4589 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129666 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129666 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446633 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554193 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 447521 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 555081 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 663080 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 663968 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16520600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16684309 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16555296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16719005 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21319765 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 505 # Total snoops (count)
-system.membus.snoop_fanout::samples 332236 # Request fanout histogram
+system.membus.pkt_size::total 21354461 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 506 # Total snoops (count)
+system.membus.snoop_fanout::samples 394644 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 332236 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 394644 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 332236 # Request fanout histogram
-system.membus.reqLayer0.occupancy 90365500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 394644 # Request fanout histogram
+system.membus.reqLayer0.occupancy 90290000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1715000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1707500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1025055153 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1026254667 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 997764949 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 999643493 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37471493 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37473491 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
sim_ticks 2827616186000 # Number of ticks simulated
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 73888 # Simulator instruction rate (inst/s)
-host_op_rate 89625 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1846444734 # Simulator tick rate (ticks/s)
-host_mem_usage 556020 # Number of bytes of host memory used
-host_seconds 1531.38 # Real time elapsed on the host
+host_inst_rate 70271 # Simulator instruction rate (inst/s)
+host_op_rate 85238 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1756065639 # Simulator tick rate (ticks/s)
+host_mem_usage 621588 # Number of bytes of host memory used
+host_seconds 1610.20 # Real time elapsed on the host
sim_insts 113151083 # Number of instructions simulated
sim_ops 137250963 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 176173 # Number of read requests accepted
+system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 176174 # Number of read requests accepted
system.physmem.writeReqs 171661 # Number of write requests accepted
-system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
+system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
system.physmem.totGap 2827615975000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 541 # Read request sizes (log2)
+system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
-system.physmem.totQLat 2104910750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2104913750 # Total ticks spent queuing
+system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
-system.physmem.avgGap 8129210.99 # Average gap between requests
+system.physmem.avgGap 8129187.62 # Average gap between requests
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
+system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
+system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
+system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25461870 # DTB read hits
+system.cpu.dtb.read_hits 25461869 # DTB read hits
system.cpu.dtb.read_misses 62291 # DTB read misses
system.cpu.dtb.write_hits 19915387 # DTB write hits
system.cpu.dtb.write_misses 10080 # DTB write misses
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25524161 # DTB read accesses
+system.cpu.dtb.read_accesses 25524160 # DTB read accesses
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45377257 # DTB hits
+system.cpu.dtb.hits 45377256 # DTB hits
system.cpu.dtb.misses 72371 # DTB misses
-system.cpu.dtb.accesses 45449628 # DTB accesses
+system.cpu.dtb.accesses 45449627 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
+system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
+system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
system.cpu.iq.rate 0.544758 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
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system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
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system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
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system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 201053 # number of nop insts executed
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system.cpu.iew.exec_branches 26530134 # Number of branches executed
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system.cpu.iew.exec_rate 0.541163 # Inst execution rate
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system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
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system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
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system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1892540 # number of replacements
system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use
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system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles
system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440466859 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440466859 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482081359 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 11870822609 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482081359 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 11870822609 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395641750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577473750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547251750 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729083750 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency
system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.811008 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.811008 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.831494 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.259057 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 62589 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.010244 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 3526784 98.98% 98.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 36501 1.02% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 68566 # Transaction distribution
-system.membus.trans_dist::ReadResp 68565 # Transaction distribution
+system.membus.trans_dist::ReadReq 68567 # Transaction distribution
+system.membus.trans_dist::ReadResp 68566 # Transaction distribution
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::Writeback 131056 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 497 # Total snoops (count)
-system.membus.snoop_fanout::samples 345038 # Request fanout histogram
+system.membus.snoop_fanout::samples 406751 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 345038 # Request fanout histogram
+system.membus.snoop_fanout::total 406751 # Request fanout histogram
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
---------- Begin Simulation Statistics ----------
-sim_seconds 2.625396 # Number of seconds simulated
-sim_ticks 2625395606000 # Number of ticks simulated
-final_tick 2625395606000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.625378 # Number of seconds simulated
+sim_ticks 2625378187500 # Number of ticks simulated
+final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93034 # Simulator instruction rate (inst/s)
-host_op_rate 112875 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2029681489 # Simulator tick rate (ticks/s)
-host_mem_usage 651304 # Number of bytes of host memory used
-host_seconds 1293.50 # Real time elapsed on the host
-sim_insts 120339436 # Number of instructions simulated
-sim_ops 146004136 # Number of ops (including micro ops) simulated
+host_inst_rate 94574 # Simulator instruction rate (inst/s)
+host_op_rate 114754 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2065319127 # Simulator tick rate (ticks/s)
+host_mem_usage 650700 # Number of bytes of host memory used
+host_seconds 1271.17 # Real time elapsed on the host
+sim_insts 120220550 # Number of instructions simulated
+sim_ops 145872273 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1180896 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1238652 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8338496 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 327120 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 750304 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 683328 # Number of bytes read from this memory
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system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
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system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
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system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s)
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 63 # Number of times write queue was full causing retry
-system.physmem.totGap 2625395343000 # Total gap between requests
+system.physmem.numWrRetry 46 # Number of times write queue was full causing retry
+system.physmem.totGap 2625377925000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 28 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::58 139 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 108 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 106 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 73 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 224 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 91717 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 247.658515 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 138.206739 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 311.047088 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 48645 53.04% 53.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18050 19.68% 72.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5879 6.41% 79.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3418 3.73% 82.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2896 3.16% 86.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1497 1.63% 87.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 939 1.02% 88.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1042 1.14% 89.80% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9351 10.20% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 91717 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6649 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 29.834862 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 569.193500 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6647 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6649 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6649 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 23.543390 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.659302 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 38.965105 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 6283 94.50% 94.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 92 1.38% 95.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 34 0.51% 96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 12 0.18% 96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 28 0.42% 96.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 36 0.54% 97.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 35 0.53% 98.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 13 0.20% 98.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 17 0.26% 98.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 4 0.06% 98.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 17 0.26% 98.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 15 0.23% 99.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 12 0.18% 99.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 2 0.03% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 5 0.08% 99.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 5 0.08% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 1 0.02% 99.43% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 2 0.03% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 5 0.08% 99.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 4 0.06% 99.59% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 13 0.20% 99.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 1 0.02% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 1 0.02% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 2 0.03% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 1 0.02% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 3 0.05% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 1 0.02% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::576-591 1 0.02% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::672-687 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::688-703 1 0.02% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.02% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6649 # Writes before turning the bus around for reads
-system.physmem.totQLat 7005041065 # Total ticks spent queuing
-system.physmem.totMemAccLat 10724572315 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 991875000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 35312.12 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads
+system.physmem.totQLat 6824061250 # Total ticks spent queuing
+system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 54062.12 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.84 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.82 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.77 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 4.29 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 27.13 # Average write queue length when enqueuing
-system.physmem.readRowHits 165504 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97693 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.43 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.40 # Row buffer hit rate for writes
-system.physmem.avgGap 6934666.38 # Average gap between requests
-system.physmem.pageHitRate 74.15 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 361050480 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 197001750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 807424800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 520687440 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 75248496990 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1509227374500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1757839822440 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.553437 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2510629171267 # Time in different power states
-system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states
+system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing
+system.physmem.readRowHits 161531 # Number of row buffer hits during reads
+system.physmem.writeRowHits 96107 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes
+system.physmem.avgGap 7118240.48 # Average gap between requests
+system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.508799 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states
+system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 27094642483 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 332330040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 181330875 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 739892400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 493691760 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 74790166545 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1509629418750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1757644616850 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.479084 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2511304272827 # Time in different power states
-system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states
+system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.445422 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states
+system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 26423733173 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 51768532 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 23412360 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 919881 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 31255966 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 23302169 # Number of BTB hits
+system.cpu0.branchPred.lookups 22612465 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 74.552708 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 15318582 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 29481 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 62660 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 62660 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24194 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18908 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 19558 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 43102 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 433.564568 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 2585.553866 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-4095 41662 96.66% 96.66% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::4096-8191 436 1.01% 97.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::8192-12287 432 1.00% 98.67% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::12288-16383 320 0.74% 99.42% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::16384-20479 76 0.18% 99.59% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::20480-24575 60 0.14% 99.73% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::24576-28671 79 0.18% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::28672-32767 9 0.02% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::32768-36863 4 0.01% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::40960-45055 16 0.04% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::45056-49151 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::49152-53247 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::57344-61439 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 43102 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 15681 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 9053.791276 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 7430.926564 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 8773.860990 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 14744 94.02% 94.02% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 873 5.57% 99.59% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 41 0.26% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-212991 10 0.06% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::212992-229375 7 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 15681 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 91363987860 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.449877 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.503999 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 91318747860 99.95% 99.95% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 34013000 0.04% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 5422000 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 3241000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 1011500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 587500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 452000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 501000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 12000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 91363987860 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 5167 76.75% 76.75% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1565 23.25% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6732 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 62660 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 61748 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 62660 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6732 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6732 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 69392 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 22710900 # DTB read hits
-system.cpu0.dtb.read_misses 53664 # DTB read misses
-system.cpu0.dtb.write_hits 16914206 # DTB write hits
-system.cpu0.dtb.write_misses 8996 # DTB write misses
+system.cpu0.dtb.read_hits 16748968 # DTB read hits
+system.cpu0.dtb.read_misses 52995 # DTB read misses
+system.cpu0.dtb.write_hits 13907664 # DTB write hits
+system.cpu0.dtb.write_misses 8753 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3521 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 84 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1885 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 828 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 22764564 # DTB read accesses
-system.cpu0.dtb.write_accesses 16923202 # DTB write accesses
+system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 16801963 # DTB read accesses
+system.cpu0.dtb.write_accesses 13916417 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 39625106 # DTB hits
-system.cpu0.dtb.misses 62660 # DTB misses
-system.cpu0.dtb.accesses 39687766 # DTB accesses
+system.cpu0.dtb.hits 30656632 # DTB hits
+system.cpu0.dtb.misses 61748 # DTB misses
+system.cpu0.dtb.accesses 30718380 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 9923 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 9923 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3743 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6075 # Level at which table walker walks with short descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 105 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 9818 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 399.113872 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 2107.706971 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-4095 9439 96.14% 96.14% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::4096-8191 239 2.43% 98.57% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::8192-12287 79 0.80% 99.38% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::12288-16383 28 0.29% 99.66% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::16384-20479 10 0.10% 99.77% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::20480-24575 11 0.11% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::28672-32767 5 0.05% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 9818 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 2687 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 10340.528470 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 8874.826622 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 6037.575177 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 928 34.54% 34.54% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1618 60.22% 94.75% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 45 1.67% 96.43% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.16% 99.59% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.85% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::57344-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 9874 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 2687 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 18349502828 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.974755 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.157116 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 463854500 2.53% 2.53% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 17885129828 97.47% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 423500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 95000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 18349502828 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 2262 87.61% 87.61% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 320 12.39% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 2582 # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9923 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2582 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2582 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 12505 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 70918524 # ITB inst hits
-system.cpu0.itb.inst_misses 9923 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 35678798 # ITB inst hits
+system.cpu0.itb.inst_misses 9874 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 70928447 # ITB inst accesses
-system.cpu0.itb.hits 70918524 # DTB hits
-system.cpu0.itb.misses 9923 # DTB misses
-system.cpu0.itb.accesses 70928447 # DTB accesses
-system.cpu0.numCycles 192710246 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses
+system.cpu0.itb.hits 35678798 # DTB hits
+system.cpu0.itb.misses 9874 # DTB misses
+system.cpu0.itb.accesses 35688672 # DTB accesses
+system.cpu0.numCycles 121733824 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 19172907 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 190300440 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 51768532 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 38620751 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 166603353 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 5605830 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 133760 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 54794 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 348448 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 420234 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 74628 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 70919147 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 257234 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 4157 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 189611039 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.227807 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.311092 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 87830492 46.32% 46.32% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 29214542 15.41% 61.73% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 14106780 7.44% 69.17% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 58459225 30.83% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 189611039 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.268634 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.987495 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 24427882 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 101305691 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 56642715 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 4754811 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 2479940 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 2942193 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 327073 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 148781526 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 3762312 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 2479940 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 32842566 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 11912016 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 79322122 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 52855770 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 10198625 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 132285921 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 1008096 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1377906 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 148604 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 51873 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 6170558 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 135790293 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 611071310 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 146878490 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 9376 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 124889963 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 10900327 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 2656202 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 2518524 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 22032615 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 23644678 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 18416726 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1638849 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2450280 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 129422072 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1660998 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 127592349 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 453825 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10488941 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 21267672 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 117222 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 189611039 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.672916 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 0.964306 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 115784330 61.06% 61.06% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 32509497 17.15% 78.21% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 29946391 15.79% 94.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 10293248 5.43% 99.43% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1077539 0.57% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 34 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 189611039 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 10302435 44.02% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 127 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 44.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 5400760 23.08% 67.10% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 7700326 32.90% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 86139109 67.51% 67.51% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 105637 0.08% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 7185 0.01% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.60% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 23381898 18.33% 85.93% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 17956248 14.07% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 127592349 # Type of FU issued
-system.cpu0.iq.rate 0.662094 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 23403648 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.183425 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 468620138 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 141579564 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 124128658 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 33072 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 11274 # Number of floating instruction queue writes
+system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued
+system.cpu0.iq.rate 0.780596 # Inst issue rate
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+system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst)
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+system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 150972031 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 21694 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 349342 # Number of loads that had data forwarded from stores
+system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1883137 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2543 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 18891 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 974261 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 112825 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 327783 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 2479940 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1553148 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 173644 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 131254258 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 23644678 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 18416726 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 851019 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 24728 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 127466 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 18891 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 275684 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 374727 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 650411 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 126563046 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 22955767 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 966765 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions
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+system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 171188 # number of nop insts executed
-system.cpu0.iew.exec_refs 40733276 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 24565455 # Number of branches executed
-system.cpu0.iew.exec_stores 17777509 # Number of stores executed
-system.cpu0.iew.exec_rate 0.656753 # Inst execution rate
-system.cpu0.iew.wb_sent 126045909 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 124138382 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 63204033 # num instructions producing a value
-system.cpu0.iew.wb_consumers 102166760 # num instructions consuming a value
+system.cpu0.iew.exec_nop 171145 # number of nop insts executed
+system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 15805524 # Number of branches executed
+system.cpu0.iew.exec_stores 14767221 # Number of stores executed
+system.cpu0.iew.exec_rate 0.772250 # Inst execution rate
+system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 48393961 # num instructions producing a value
+system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.644171 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.618636 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 9496881 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1543776 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 596906 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 186488308 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.647310 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.345681 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 128655160 68.99% 68.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 31929494 17.12% 86.11% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 12238036 6.56% 92.67% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 3079239 1.65% 94.32% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 4650991 2.49% 96.82% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 2566190 1.38% 98.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1394957 0.75% 98.94% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 526048 0.28% 99.22% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1448193 0.78% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 186488308 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 99634335 # Number of instructions committed
-system.cpu0.commit.committedOps 120715819 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 74499569 # Number of instructions committed
+system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 39204006 # Number of memory references committed
-system.cpu0.commit.loads 21761541 # Number of loads committed
-system.cpu0.commit.membars 628761 # Number of memory barriers committed
-system.cpu0.commit.branches 23967170 # Number of branches committed
+system.cpu0.commit.refs 30256494 # Number of memory references committed
+system.cpu0.commit.loads 15822807 # Number of loads committed
+system.cpu0.commit.membars 627513 # Number of memory barriers committed
+system.cpu0.commit.branches 15208996 # Number of branches committed
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 105564175 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 4749359 # Number of function calls committed.
+system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 1847857 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 81401150 67.43% 67.43% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 103478 0.09% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 7185 0.01% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 21761541 18.03% 85.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 17442465 14.45% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction
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-system.cpu0.committedOps 120594125 # Number of Ops (including micro ops) Simulated
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-system.cpu0.cpi_total 1.936540 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.516385 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.516385 # IPC: Total IPC of All Threads
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 14326.228083 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13529.416009 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13529.416009 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 842 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 3715311 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 190617 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 17.541667 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 19.490974 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 491598 # number of writebacks
-system.cpu0.dcache.writebacks::total 491598 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 240080 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 240080 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1488537 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1488537 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18067 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18067 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1728617 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1728617 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1728617 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1728617 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366505 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 366505 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312052 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 312052 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98413 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 98413 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6200 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6200 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21226 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 21226 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 678557 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 678557 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 776970 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 776970 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4125978302 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4125978302 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5242118761 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5242118761 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570027702 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570027702 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 93210251 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93210251 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 452955960 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 452955960 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 405000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 405000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9368097063 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9368097063 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10938124765 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10938124765 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5613897000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5613897000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4260937012 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4260937012 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9874834012 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9874834012 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017253 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019273 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019273 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224574 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224574 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016357 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016357 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056944 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056944 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018127 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.018127 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020516 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.020516 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11257.631689 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11257.631689 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16798.862885 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16798.862885 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15953.458405 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15953.458405 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15033.911452 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15033.911452 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21339.675869 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21339.675869 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks
+system.cpu0.dcache.writebacks::total 492000 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits
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+system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13805.910282 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13805.910282 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14077.924199 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14077.924199 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1204763 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.748349 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 69666497 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1205275 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 57.801329 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6415532250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748349 # Average occupied blocks per requestor
+system.cpu0.icache.tags.replacements 1200530 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 144 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 143036633 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 143036633 # Number of data accesses
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-system.cpu0.icache.ReadReq_hits::total 69666497 # number of ReadReq hits
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
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-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 17.267794 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.026625 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4039.749605 # Average occupied blocks per requestor
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system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id
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-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4060847435 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4060847435 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9439227935 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9680752685 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.207588 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.085328 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000002 # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000002 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.490488 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.490488 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924472 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924472 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155164 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155164 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094304 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008377 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013975 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041497 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189106 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210650 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22380.478778 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29128.987054 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65232.824954 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19483.134431 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19483.134431 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14962.568676 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14962.568676 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 160999.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 160999.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40778.326071 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40778.326071 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31592.482214 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20474.646226 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17525.147929 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42434.451935 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27702.324875 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65232.824954 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50172.703537 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1908189 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1835262 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 26172 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 26172 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 491597 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 299764 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 91875 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43573 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 114693 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 284602 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 270315 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2416584 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2311982 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27986 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112626 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4869178 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77186016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82205272 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 48372 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202464 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 159642124 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 659500 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3123483 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.174208 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.379288 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 687931 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 2579348 82.58% 82.58% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 544135 17.42% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3123483 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1823730646 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 112580498 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1815085939 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1180413157 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 15906731 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 62058933 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 6179090 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 3881916 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 362855 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 3346788 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 2458848 # Number of BTB hits
+system.cpu1.branchPred.lookups 35319893 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 12619406 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 73.468890 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 1048082 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 10606 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 24514 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 24514 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11457 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6002 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 7055 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 17459 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 393.464689 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 2513.400268 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-4095 16937 97.01% 97.01% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::4096-8191 156 0.89% 97.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::8192-12287 187 1.07% 98.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::12288-16383 85 0.49% 99.46% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::16384-20479 23 0.13% 99.59% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::20480-24575 6 0.03% 99.63% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::24576-28671 44 0.25% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::28672-32767 3 0.02% 99.90% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 24259 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 17459 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 5476 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 9377.190285 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 8039.034346 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 5934.391980 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-8191 2488 45.43% 45.43% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2481 45.31% 90.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-24575 381 6.96% 97.70% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-32767 96 1.75% 99.45% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-40959 6 0.11% 99.56% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::40960-49151 20 0.37% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 5476 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 69614954880 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.366193 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.484439 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 44157971700 63.43% 63.43% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 25439149180 36.54% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2 11249000 0.02% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::3 3199000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4 940000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::5 768000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6 744500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::7 290500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8 107000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::9 122500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10 85500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::11 64000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12 71500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::13 26500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14 31000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::15 135000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 69614954880 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1964 73.78% 73.78% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 698 26.22% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2662 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24514 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24514 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2662 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2662 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 27176 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 5241297 # DTB read hits
-system.cpu1.dtb.read_misses 21288 # DTB read misses
-system.cpu1.dtb.write_hits 4318497 # DTB write hits
-system.cpu1.dtb.write_misses 3226 # DTB write misses
+system.cpu1.dtb.read_hits 11166498 # DTB read hits
+system.cpu1.dtb.read_misses 21069 # DTB read misses
+system.cpu1.dtb.write_hits 7306223 # DTB write hits
+system.cpu1.dtb.write_misses 3190 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 72 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 621 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 379 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 5262585 # DTB read accesses
-system.cpu1.dtb.write_accesses 4321723 # DTB write accesses
+system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 11187567 # DTB read accesses
+system.cpu1.dtb.write_accesses 7309413 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 9559794 # DTB hits
-system.cpu1.dtb.misses 24514 # DTB misses
-system.cpu1.dtb.accesses 9584308 # DTB accesses
+system.cpu1.dtb.hits 18472721 # DTB hits
+system.cpu1.dtb.misses 24259 # DTB misses
+system.cpu1.dtb.accesses 18496980 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 6863 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 6863 # Table walker walks initiated with short descriptors
-system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4096 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2697 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 70 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 6793 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 193.655233 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 1558.039702 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-2047 6647 97.85% 97.85% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::2048-4095 36 0.53% 98.38% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 98.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::6144-8191 24 0.35% 99.15% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::8192-10239 16 0.24% 99.38% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::10240-12287 12 0.18% 99.56% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::12288-14335 8 0.12% 99.68% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::14336-16383 5 0.07% 99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::16384-18431 3 0.04% 99.79% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::18432-20479 3 0.04% 99.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.87% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::22528-24575 4 0.06% 99.93% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::26624-28671 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::30720-32767 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 6793 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 1235 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 10095.547368 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 8796.441001 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5908.625766 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095 181 14.66% 14.66% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.17% 28.83% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 552 44.70% 73.52% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 256 20.73% 94.25% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 7 0.57% 94.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::20480-24575 7 0.57% 95.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.27% 97.65% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 18 1.46% 99.11% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-36863 3 0.24% 99.35% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.40% 99.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.16% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 6817 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 1235 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 18043801328 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.988843 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.105174 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 201557764 1.12% 1.12% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 17842013064 98.88% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 213500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 17000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 18043801328 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6863 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6863 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 8028 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 10532607 # ITB inst hits
-system.cpu1.itb.inst_misses 6863 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 45723303 # ITB inst hits
+system.cpu1.itb.inst_misses 6817 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1195 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 10539470 # ITB inst accesses
-system.cpu1.itb.hits 10532607 # DTB hits
-system.cpu1.itb.misses 6863 # DTB misses
-system.cpu1.itb.accesses 10539470 # DTB accesses
-system.cpu1.numCycles 43132973 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses
+system.cpu1.itb.hits 45723303 # DTB hits
+system.cpu1.itb.misses 6817 # DTB misses
+system.cpu1.itb.accesses 45730120 # DTB accesses
+system.cpu1.numCycles 113567718 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 9545781 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 31669827 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 6179090 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 3506930 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 31408441 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 995212 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 85708 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 38872 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 217286 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 331419 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 27804 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 10531999 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 133008 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2352 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 42152917 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.913975 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.225517 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 35319893 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 24362526 57.80% 57.80% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 6315176 14.98% 72.78% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 2214119 5.25% 78.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 9261096 21.97% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 42152917 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.143257 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.734237 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 8274124 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 20645023 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 11553748 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1337865 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 342157 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 880050 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 158552 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 30233981 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 1392367 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 342157 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 10058392 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2609511 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 14923378 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 11073163 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 3146316 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 28748329 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 284293 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 329352 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 50565 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 19779 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 1931384 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 29150261 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 132893523 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 32973401 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 1672 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 25705063 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 3445198 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 453540 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 375844 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 3445196 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 5586646 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 4747027 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 699100 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 721726 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 27759685 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 627473 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 27258527 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 145234 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2977146 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 6943190 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 53970 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 42152917 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.646658 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.966330 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 26379254 62.58% 62.58% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 7348926 17.43% 80.01% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 5684884 13.49% 93.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 2419597 5.74% 99.24% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 320238 0.76% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 42152917 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2004888 32.52% 32.52% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 611 0.01% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.53% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 1891782 30.69% 63.22% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 2267092 36.78% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 17154225 62.93% 62.93% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 35391 0.13% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 1 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 4079 0.01% 63.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.08% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 5491685 20.15% 83.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 4573079 16.78% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 27258527 # Type of FU issued
-system.cpu1.iq.rate 0.631965 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 6164373 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.226145 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 102973934 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 31372858 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 26623969 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 5644 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 2050 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 1785 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 33419259 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 3574 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 107638 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued
+system.cpu1.iq.rate 0.525478 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 606025 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 849 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 10642 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 402770 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 45923 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 97906 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 342157 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 666539 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 117242 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 28442190 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 5586646 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 4747027 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 329140 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 12736 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 94970 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 10642 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 72014 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 152187 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 224201 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 26920844 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 5360548 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 313188 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 55032 # number of nop insts executed
-system.cpu1.iew.exec_refs 9857010 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 4125375 # Number of branches executed
-system.cpu1.iew.exec_stores 4496462 # Number of stores executed
-system.cpu1.iew.exec_rate 0.624136 # Inst execution rate
-system.cpu1.iew.wb_sent 26746276 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 26625754 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 13483465 # num instructions producing a value
-system.cpu1.iew.wb_consumers 21315020 # num instructions consuming a value
+system.cpu1.iew.exec_nop 55192 # number of nop insts executed
+system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 12866831 # Number of branches executed
+system.cpu1.iew.exec_stores 7487148 # Number of stores executed
+system.cpu1.iew.exec_rate 0.522399 # Inst execution rate
+system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 28211344 # num instructions producing a value
+system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.617295 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.632580 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 2680688 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 573503 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 207406 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 41589167 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.611775 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.358099 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 29454101 70.82% 70.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 7064012 16.99% 87.81% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 2119517 5.10% 92.90% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 873586 2.10% 95.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 770133 1.85% 96.86% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 442153 1.06% 97.92% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 274514 0.66% 98.58% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 148169 0.36% 98.93% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 442982 1.07% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 41589167 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 20860008 # Number of instructions committed
-system.cpu1.commit.committedOps 25443224 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 45875888 # Number of instructions committed
+system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 9324878 # Number of memory references committed
-system.cpu1.commit.loads 4980621 # Number of loads committed
-system.cpu1.commit.membars 230323 # Number of memory barriers committed
-system.cpu1.commit.branches 3917567 # Number of branches committed
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+system.cpu1.commit.membars 231720 # Number of memory barriers committed
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system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 22363157 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 552505 # Number of function calls committed.
+system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions.
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system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.33% # Class of committed instruction
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-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.33% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 4079 0.02% 63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.35% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 4980621 19.58% 82.93% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 4344257 17.07% 100.00% # Class of committed instruction
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-system.cpu1.idleCycles 980056 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 5207108948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 20826795 # Number of Instructions Simulated
-system.cpu1.committedOps 25410011 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 2.071033 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.071033 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.482851 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.482851 # IPC: Total IPC of All Threads
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-system.cpu1.dcache.tags.avg_refs 36.830537 # Average number of references to valid blocks.
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+system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads
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-system.cpu1.dcache.SoftPFReq_hits::total 63652 # number of SoftPFReq hits
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15858.806812 # average ReadReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19533.151897 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23289.574993 # average StoreCondReq miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19678.116168 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 19678.116168 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 375 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 1600979 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 49143 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.363636 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 32.577966 # average number of cycles each access was blocked
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system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 137785 # number of writebacks
-system.cpu1.dcache.writebacks::total 137785 # number of writebacks
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13259.009060 # average ReadReq mshr miss latency
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-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21740.907361 # average StoreCondReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
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-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17808.346876 # average overall mshr miss latency
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-system.cpu1.icache.tags.warmup_cycle 78865217000 # Cycle when the warmup percentage was hit.
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-system.cpu1.icache.ReadReq_mshr_hits::total 22831 # number of ReadReq MSHR hits
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-system.cpu1.icache.demand_mshr_miss_latency::total 5443930957 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5443930957 # number of overall MSHR miss cycles
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-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 8150.512343 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8150.512343 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034164 # mshr miss rate for demand accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393035 # mshr miss rate for demand accesses
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15629.840547 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21082.676715 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43292.975324 # average HardPFReq mshr miss latency
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-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16624.510045 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14959.086955 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14959.086955 # average SCUpgradeReq mshr miss latency
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-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34156.951863 # average overall mshr miss latency
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-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1243272 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 949021 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 4907 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 4907 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 137784 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 47376 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 75841 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43101 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 89718 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 96830 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 79934 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1336034 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 901614 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17159 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 43403 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2298210 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42747664 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29480945 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 79768 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 72339053 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 592219 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1674781 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.301785 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.459032 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution
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system.iobus.trans_dist::ReadResp 31011 # Transaction distribution
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system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 213069 # Transaction distribution
-system.membus.trans_dist::ReadResp 213068 # Transaction distribution
-system.membus.trans_dist::WriteReq 31079 # Transaction distribution
-system.membus.trans_dist::WriteResp 31079 # Transaction distribution
-system.membus.trans_dist::Writeback 139403 # Transaction distribution
+system.membus.trans_dist::ReadReq 209523 # Transaction distribution
+system.membus.trans_dist::ReadResp 209522 # Transaction distribution
+system.membus.trans_dist::WriteReq 31055 # Transaction distribution
+system.membus.trans_dist::WriteResp 31055 # Transaction distribution
+system.membus.trans_dist::Writeback 134913 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 77234 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 14409 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
-system.membus.trans_dist::ReadExReq 40484 # Transaction distribution
-system.membus.trans_dist::ReadExResp 20462 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
+system.membus.trans_dist::ReadExReq 38508 # Transaction distribution
+system.membus.trans_dist::ReadExResp 18805 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14202 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 662750 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 784904 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 893825 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28404 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19143964 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19335481 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23971961 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 125081 # Total snoops (count)
-system.membus.snoop_fanout::samples 510035 # Request fanout histogram
+system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 125464 # Total snoops (count)
+system.membus.snoop_fanout::samples 569969 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 510035 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 510035 # Request fanout histogram
-system.membus.reqLayer0.occupancy 81680000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 569969 # Request fanout histogram
+system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11944988 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1164089698 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1154561869 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37506493 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 494432 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 494416 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31079 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31079 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 232253 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36258 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 80398 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41961 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 122359 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 30 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 50963 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 50963 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1036150 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 339974 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1376124 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31294456 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6755201 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 38049657 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 290334 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 898197 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.040648 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.197474 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 292587 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 861687 95.94% 95.94% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36510 4.06% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 898197 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 772973190 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 636594669 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 265283017 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2748 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
sim_ticks 2827616186000 # Number of ticks simulated
final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 94820 # Simulator instruction rate (inst/s)
-host_op_rate 115016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2369528287 # Simulator tick rate (ticks/s)
-host_mem_usage 555256 # Number of bytes of host memory used
-host_seconds 1193.32 # Real time elapsed on the host
+host_inst_rate 97479 # Simulator instruction rate (inst/s)
+host_op_rate 118241 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2435971946 # Simulator tick rate (ticks/s)
+host_mem_usage 621864 # Number of bytes of host memory used
+host_seconds 1160.78 # Real time elapsed on the host
sim_insts 113151083 # Number of instructions simulated
sim_ops 137250963 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory
system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 176173 # Number of read requests accepted
+system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 176174 # Number of read requests accepted
system.physmem.writeReqs 171661 # Number of write requests accepted
-system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue
+system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue
system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11334 # Per bank write bursts
system.physmem.totGap 2827615975000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 541 # Read request sizes (log2)
+system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 2994 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads
-system.physmem.totQLat 2104910750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2104913750 # Total ticks spent queuing
+system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s
system.physmem.writeRowHits 112529 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes
-system.physmem.avgGap 8129210.99 # Average gap between requests
+system.physmem.avgGap 8129187.62 # Average gap between requests
system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ)
+system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ)
system.physmem_0.averagePower 669.422846 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states
system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ)
+system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ)
system.physmem_1.averagePower 669.324331 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states
+system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states
system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25461870 # DTB read hits
+system.cpu.dtb.read_hits 25461869 # DTB read hits
system.cpu.dtb.read_misses 62291 # DTB read misses
system.cpu.dtb.write_hits 19915387 # DTB write hits
system.cpu.dtb.write_misses 10080 # DTB write misses
system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25524161 # DTB read accesses
+system.cpu.dtb.read_accesses 25524160 # DTB read accesses
system.cpu.dtb.write_accesses 19925467 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45377257 # DTB hits
+system.cpu.dtb.hits 45377256 # DTB hits
system.cpu.dtb.misses 72371 # DTB misses
-system.cpu.dtb.accesses 45449628 # DTB accesses
+system.cpu.dtb.accesses 45449627 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst
+system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking
+system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename
system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full
+system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full
system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups
system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued
+system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued
+system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued
system.cpu.iq.rate 0.544758 # Inst issue rate
system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing
system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed
+system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 201053 # number of nop insts executed
-system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed
+system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed
system.cpu.iew.exec_branches 26530134 # Number of branches executed
system.cpu.iew.exec_stores 20877849 # Number of stores executed
system.cpu.iew.exec_rate 0.541163 # Inst execution rate
-system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit
+system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back
system.cpu.iew.wb_producers 63271750 # num instructions producing a value
system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value
system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads
system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155826637 # number of integer regfile reads
+system.cpu.int_regfile_reads 155826636 # number of integer regfile reads
system.cpu.int_regfile_writes 88633021 # number of integer regfile writes
system.cpu.fp_regfile_reads 9606 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads
+system.cpu.cc_regfile_reads 502981878 # number of cc regfile reads
system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes
-system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads
+system.cpu.misc_regfile_reads 446088160 # number of misc regfile reads
system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes
system.cpu.dcache.tags.replacements 839617 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use
system.cpu.dcache.overall_misses::total 4478306 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502760344 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 149502760344 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles
system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 159775872007 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 159775872007 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 159775872007 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 159775872007 # number of overall miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.568194 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.568194 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency
system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked
system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235278165 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles
system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.189793 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.189793 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency
system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution
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system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
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system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::Writeback 131056 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 497 # Total snoops (count)
-system.membus.snoop_fanout::samples 345038 # Request fanout histogram
+system.membus.snoop_fanout::samples 406751 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 345038 # Request fanout histogram
+system.membus.snoop_fanout::total 406751 # Request fanout histogram
system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
sim_ticks 2817777605000 # Number of ticks simulated
final_tick 2817777605000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 278686 # Simulator instruction rate (inst/s)
-host_op_rate 338399 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6220604315 # Simulator tick rate (ticks/s)
-host_mem_usage 555292 # Number of bytes of host memory used
-host_seconds 452.98 # Real time elapsed on the host
+host_inst_rate 294801 # Simulator instruction rate (inst/s)
+host_op_rate 357967 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6580315461 # Simulator tick rate (ticks/s)
+host_mem_usage 623656 # Number of bytes of host memory used
+host_seconds 428.21 # Real time elapsed on the host
sim_insts 126237777 # Number of instructions simulated
sim_ops 153286368 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.overall_mshr_misses::cpu1.data 114514 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 322025 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 436539 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 823130250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2155055358 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2978185608 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21649.046667 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26000.062865 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24858.693436 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177408.078231 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 196862.425863 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 188961.910353 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174550.967181 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 194575.011129 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186450.617284 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 176153.849823 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 195857.412961 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 187858.921724 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1799096 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.534039 # Cycle average of tags in use
system.l2c.overall_mshr_misses::cpu2.inst 8124 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 64429 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 91595 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5880 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8599 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 14479 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4601 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data 6739 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 11340 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10481 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data 15338 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 25819 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 132598250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 173127242 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71458.148695 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69541.309084 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 69076.292636 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163404.166667 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182859.169671 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 174958.388010 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161549.228429 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181573.304645 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173448.897707 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 162589.876920 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 182294.203938 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 174295.402610 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 74250 # Transaction distribution
system.membus.trans_dist::ReadResp 74249 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 4642624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 21734523 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 283 # Total snoops (count)
-system.membus.snoop_fanout::samples 341064 # Request fanout histogram
+system.membus.snoop_fanout::samples 408724 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 341064 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 408724 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 341064 # Request fanout histogram
+system.membus.snoop_fanout::total 408724 # Request fanout histogram
system.membus.reqLayer0.occupancy 45631500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 463000 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 154828 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 213072335 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 51752 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3427725 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.010649 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.102642 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3495385 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.029269 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.168561 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3391224 98.94% 98.94% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 36501 1.06% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3393077 97.07% 97.07% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 102308 2.93% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3427725 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3495385 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 1275217471 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 177000 # Layer occupancy (ticks)
sim_ticks 2804323403500 # Number of ticks simulated
final_tick 2804323403500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 105186 # Simulator instruction rate (inst/s)
-host_op_rate 127668 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2521360773 # Simulator tick rate (ticks/s)
-host_mem_usage 559780 # Number of bytes of host memory used
-host_seconds 1112.23 # Real time elapsed on the host
+host_inst_rate 111575 # Simulator instruction rate (inst/s)
+host_op_rate 135423 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2674508102 # Simulator tick rate (ticks/s)
+host_mem_usage 626368 # Number of bytes of host memory used
+host_seconds 1048.54 # Real time elapsed on the host
sim_insts 116990114 # Number of instructions simulated
sim_ops 141995948 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytes_read::cpu0.data 4989088 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 4032 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 687552 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 4838852 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 4838856 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11215652 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11215656 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 690752 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 687552 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1378304 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu0.data 78473 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 63 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 10743 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 75608 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 75609 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 175764 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 175765 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 131657 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.data 1779070 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 1438 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 245176 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 1725497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 1725499 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 342 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3999415 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3999416 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 246317 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 245176 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 491493 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 1785316 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 1438 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 245176 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 1725500 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 1725501 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 342 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7010327 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 175765 # Number of read requests accepted
+system.physmem.bw_total::total 7010328 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 175766 # Number of read requests accepted
system.physmem.writeReqs 172232 # Number of write requests accepted
-system.physmem.readBursts 175765 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 175766 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 172232 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 11239872 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9088 # Total number of bytes read from write queue
+system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
system.physmem.bytesWritten 9513088 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11215716 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 11215720 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 10759988 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 142 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 23563 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4633 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 11568 # Per bank write bursts
system.physmem.totGap 2804323239500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 541 # Read request sizes (log2)
+system.physmem.readPktSize::2 542 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.wrPerTurnAround::544-559 6 0.10% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::608-623 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6306 # Writes before turning the bus around for reads
-system.physmem.totQLat 2686689750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5979621000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 2686692750 # Total ticks spent queuing
+system.physmem.totMemAccLat 5979624000 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 878115000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 15298.05 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 15298.07 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 34048.05 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 34048.07 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s
system.physmem.writeRowHits 112992 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.73 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 76.00 # Row buffer hit rate for writes
-system.physmem.avgGap 8058469.58 # Average gap between requests
+system.physmem.avgGap 8058446.43 # Average gap between requests
system.physmem.pageHitRate 79.65 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 264138840 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 144123375 # Energy for precharge commands per rank (pJ)
system.cpu0.dcache.overall_mshr_misses::cpu0.data 427411 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 420424 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 847835 # number of overall MSHR misses
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+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 14569 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable
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+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11418 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable
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+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 25987 # number of overall MSHR uncacheable misses
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2911652660 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2946522646 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5858175306 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 10511181656 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 21311507836 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3107181500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733312000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840493500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2733353000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5840534500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2374455377 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2136736500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4511191877 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5481636877 # number of overall MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351685377 # number of overall MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10351726377 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016596 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015934 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016259 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 25269.181607 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 25001.383499 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 25136.386014 # average overall mshr miss latency
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-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 187614.318073 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187635.637871 # average ReadReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176316.642145 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1944350 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.567211 # Cycle average of tags in use
system.cpu0.icache.overall_misses::cpu1.inst 1047869 # number of overall misses
system.cpu0.icache.overall_misses::total 2088934 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14016266373 # number of ReadReq miss cycles
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system.cpu0.icache.demand_miss_latency::cpu0.inst 14016266373 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 14162864905 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 28179131278 # number of demand (read+write) miss cycles
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system.cpu0.icache.overall_miss_latency::cpu0.inst 14016266373 # number of overall miss cycles
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-system.cpu0.icache.overall_miss_latency::total 28179131278 # number of overall miss cycles
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system.cpu0.icache.ReadReq_accesses::cpu0.inst 20232960 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 20978073 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 41211033 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.049951 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.050689 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13463.392173 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13515.873554 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13489.718334 # average ReadReq miss latency
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system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13463.392173 # average overall miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 13489.718334 # average overall miss latency
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-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.873554 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13489.718334 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13515.876417 # average overall miss latency
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system.cpu0.icache.blocked_cycles::no_mshrs 10636 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 597 # number of cycles access was blocked
system.cpu0.icache.overall_mshr_misses::cpu0.inst 969720 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 975231 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1944951 # number of overall MSHR misses
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+system.cpu0.icache.ReadReq_mshr_uncacheable::total 666 # number of ReadReq MSHR uncacheable
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system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11896534814 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.demand_mshr_miss_latency::total 23909245372 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 12012713558 # number of demand (read+write) MSHR miss cycles
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system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11896534814 # number of overall MSHR miss cycles
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 52863250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 52863250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 52863250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.046488 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.047195 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12292.980837 # average ReadReq mshr miss latency
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system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12292.980837 # average overall mshr miss latency
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system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12268.010162 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.810404 # average overall mshr miss latency
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-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12317.813480 # average overall mshr miss latency
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+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 79374.249249 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 79374.249249 # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 79374.249249 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.branchPred.lookups 27831531 # Number of BP lookups
system.cpu1.branchPred.condPredicted 14488346 # Number of conditional branches predicted
system.cpu1.dtb.walker.walkRequestOrigin::total 63374 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 14522718 # DTB read hits
+system.cpu1.dtb.read_hits 14522717 # DTB read hits
system.cpu1.dtb.read_misses 49745 # DTB read misses
system.cpu1.dtb.write_hits 10695995 # DTB write hits
system.cpu1.dtb.write_misses 8403 # DTB write misses
system.cpu1.dtb.prefetch_faults 1213 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 578 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 14572463 # DTB read accesses
+system.cpu1.dtb.read_accesses 14572462 # DTB read accesses
system.cpu1.dtb.write_accesses 10704398 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 25218713 # DTB hits
+system.cpu1.dtb.hits 25218712 # DTB hits
system.cpu1.dtb.misses 58148 # DTB misses
-system.cpu1.dtb.accesses 25276861 # DTB accesses
+system.cpu1.dtb.accesses 25276860 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.fetch.Insts 108613899 # Number of instructions fetch has processed
system.cpu1.fetch.Branches 27831531 # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches 19968612 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 63156516 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.Cycles 63156510 # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles 3276855 # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles 120748 # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles 7463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.CacheLines 20978077 # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes 379105 # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes 3473 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 106194794 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::samples 106194788 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean 1.229505 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev 2.326126 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 76382369 71.93% 71.93% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 76382363 71.93% 71.93% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1 3967856 3.74% 75.66% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2 2509209 2.36% 78.03% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3 8248224 7.77% 85.79% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 106194794 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::total 106194788 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate 0.255909 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.998697 # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles 27865394 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 59086639 # Number of cycles decode is blocked
+system.cpu1.decode.BlockedCycles 59086633 # Number of cycles decode is blocked
system.cpu1.decode.RunCycles 16014101 # Number of cycles decode is running
system.cpu1.decode.UnblockCycles 1741536 # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles 1486862 # Number of cycles decode is squashing
system.cpu1.rename.SquashCycles 1486862 # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles 28829421 # Number of cycles rename is idle
system.cpu1.rename.BlockCycles 4993628 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 46364709 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.serializeStallCycles 46364703 # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles 16784538 # Number of cycles rename is running
system.cpu1.rename.UnblockCycles 7735362 # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts 86665296 # Number of instructions processed by rename
system.cpu1.memDep0.conflictingStores 2888870 # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded 83375619 # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded 1158159 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 79910900 # Number of instructions issued
+system.cpu1.iq.iqInstsIssued 79910899 # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued 92494 # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined 11441232 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined 25615832 # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved 107265 # Number of squashed non-spec instructions that were removed
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system.cpu1.iq.issued_per_cycle::mean 0.752494 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev 1.434563 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::2 8178605 7.70% 87.62% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3 6800959 6.40% 94.03% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4 2513016 2.37% 96.39% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
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+system.cpu1.iq.issued_per_cycle::total 106194788 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu 110018 9.66% 9.66% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult 6 0.00% 9.66% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 67.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 67.14% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.14% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 14931901 18.69% 85.82% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 14931900 18.69% 85.82% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite 11328871 14.18% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 79910900 # Type of FU issued
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system.cpu1.iq.rate 0.734775 # Inst issue rate
system.cpu1.iq.fu_busy_cnt 1139082 # FU busy when requested
system.cpu1.iq.fu_busy_rate 0.014254 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 267236211 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_reads 267236203 # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes 96019084 # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses 77543645 # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads 11959 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 6290 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 5191 # Number of floating instruction queue wakeup accesses
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system.cpu1.iq.fp_alu_accesses 6453 # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads 351971 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedStores 1138977 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 192559 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.rescheduledLoads 192557 # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked 108870 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles 1486862 # Number of cycles IEW is squashing
system.cpu1.iew.iewIQFullEvents 42277 # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents 608480 # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents 51509 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 260306 # Number of branches that were predicted taken incorrectly
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system.cpu1.iew.predictedNotTakenIncorrect 223242 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 483548 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 79294807 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 14687603 # Number of load instructions executed
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system.cpu1.iew.iewExecSquashedInsts 558095 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
system.cpu1.iew.exec_nop 123637 # number of nop insts executed
-system.cpu1.iew.exec_refs 25906138 # number of memory reference insts executed
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system.cpu1.iew.exec_branches 14775343 # Number of branches executed
system.cpu1.iew.exec_stores 11218535 # Number of stores executed
system.cpu1.iew.exec_rate 0.729110 # Inst execution rate
-system.cpu1.iew.wb_sent 78721985 # cumulative count of insts sent to commit
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system.cpu1.iew.wb_count 77548836 # cumulative count of insts written-back
system.cpu1.iew.wb_producers 40818570 # num instructions producing a value
system.cpu1.iew.wb_consumers 71550295 # num instructions consuming a value
system.cpu1.commit.commitSquashedInsts 11482053 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 1050894 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 406174 # The number of times a branch was mispredicted
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system.cpu1.commit.committed_per_cycle::1 12628786 12.19% 84.78% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2 6551089 6.32% 91.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3 2721278 2.63% 93.72% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
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system.cpu1.commit.committedInsts 60426665 # Number of instructions committed
system.cpu1.commit.committedOps 73162446 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total 73162446 # Class of committed instruction
system.cpu1.commit.bw_lim_events 1807529 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 173729023 # The number of ROB reads
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system.cpu1.rob.rob_writes 171875858 # The number of ROB writes
system.cpu1.timesIdled 390006 # Number of times that the entire CPU went into an idle state and unscheduled itself
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system.cpu1.quiesceCycles 2437360736 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 60356761 # Number of Instructions Simulated
system.cpu1.committedOps 73092542 # Number of Ops (including micro ops) Simulated
system.cpu1.cpi_total 1.801880 # CPI: Total CPI of All Threads
system.cpu1.ipc 0.554976 # IPC: Instructions Per Cycle
system.cpu1.ipc_total 0.554976 # IPC: Total IPC of All Threads
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system.cpu1.int_regfile_writes 49415173 # number of integer regfile writes
system.cpu1.fp_regfile_reads 15994 # number of floating regfile reads
system.cpu1.fp_regfile_writes 13022 # number of floating regfile writes
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system.cpu1.cc_regfile_writes 29562027 # number of cc regfile writes
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system.cpu1.misc_regfile_writes 795609 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30198 # Transaction distribution
system.iobus.trans_dist::ReadResp 30198 # Transaction distribution
system.l2c.ReadReq_miss_latency::cpu0.inst 835233999 # number of ReadReq miss cycles
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system.l2c.UpgradeReq_miss_latency::total 843973 # number of UpgradeReq miss cycles
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system.l2c.ReadReq_avg_miss_latency::cpu0.data 86473.276228 # average ReadReq miss latency
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system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 317.710383 # average UpgradeReq miss latency
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system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
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+system.l2c.overall_mshr_uncacheable_latency::total 9595836749 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.001866 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000121 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.010457 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 74173.833715 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76178.093645 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.458837 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 72371.541995 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17857.158293 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17759.001561 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.167520 # average UpgradeReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 74533.088235 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 56250 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69835.585265 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 71488.206683 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74690.476190 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.184847 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70706.464073 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71311.543968 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 71271.402236 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::total 71271.419213 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 173633.138060 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173608.689684 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171279.440411 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 133743.257454 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174133.473463 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150462.206352 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 61808.932432 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 153927.117712 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 173839.265787 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 161608.648955 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 68117 # Transaction distribution
-system.membus.trans_dist::ReadResp 68116 # Transaction distribution
+system.membus.trans_dist::ReadReq 68118 # Transaction distribution
+system.membus.trans_dist::ReadResp 68117 # Transaction distribution
system.membus.trans_dist::WriteReq 27584 # Transaction distribution
system.membus.trans_dist::WriteResp 27584 # Transaction distribution
system.membus.trans_dist::Writeback 131657 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465311 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 572879 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 465313 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 572881 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108814 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108814 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 681693 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 681695 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344024 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17507929 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17344028 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17507933 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4631616 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4631616 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22139545 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22139549 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 523 # Total snoops (count)
-system.membus.snoop_fanout::samples 347614 # Request fanout histogram
+system.membus.snoop_fanout::samples 406994 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 347614 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 406994 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 347614 # Request fanout histogram
+system.membus.snoop_fanout::total 406994 # Request fanout histogram
system.membus.reqLayer0.occupancy 95655500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 16812 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 1658000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1067095796 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1067096296 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1022748121 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1022750121 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer3.occupancy 37540981 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 2657013 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2656927 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 2657014 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2656928 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 704443 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 296803 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 296803 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891000 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536659 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2536661 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42360 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169075 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 6639094 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6639096 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124504512 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962073 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99962077 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 64700 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 291504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 224822789 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 224822793 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 70210 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3665576 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.009952 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.099262 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3724954 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.042649 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.202064 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3629096 99.00% 99.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 36480 1.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3566090 95.74% 95.74% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 158864 4.26% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3665576 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2562503934 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3724954 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2562504434 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 246000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 2923288858 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 1353662761 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 1353663761 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 26203715 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
---------- Begin Simulation Statistics ----------
-sim_seconds 47.443139 # Number of seconds simulated
-sim_ticks 47443139283500 # Number of ticks simulated
-final_tick 47443139283500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.365947 # Number of seconds simulated
+sim_ticks 47365946685500 # Number of ticks simulated
+final_tick 47365946685500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 174986 # Simulator instruction rate (inst/s)
-host_op_rate 205797 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 9320406551 # Simulator tick rate (ticks/s)
-host_mem_usage 765676 # Number of bytes of host memory used
-host_seconds 5090.24 # Real time elapsed on the host
-sim_insts 890723033 # Number of instructions simulated
-sim_ops 1047557701 # Number of ops (including micro ops) simulated
+host_inst_rate 174192 # Simulator instruction rate (inst/s)
+host_op_rate 204861 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9672451523 # Simulator tick rate (ticks/s)
+host_mem_usage 763596 # Number of bytes of host memory used
+host_seconds 4897.00 # Real time elapsed on the host
+sim_insts 853019792 # Number of instructions simulated
+sim_ops 1003201701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 111744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 91648 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 7668224 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 13156952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 13340800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 149248 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 146240 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 3865344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 11856672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 13765376 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 430976 # Number of bytes read from this memory
-system.physmem.bytes_read::total 64583224 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 7668224 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 3865344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 11533568 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75782720 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 65472 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 64384 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 7833792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 12003144 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766848 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 71104 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 69248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 2839488 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 7678416 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 7994432 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 439552 # Number of bytes read from this memory
+system.physmem.bytes_read::total 49825880 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 7833792 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 2839488 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 10673280 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 62800512 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
-system.physmem.bytes_written::total 75803536 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1746 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1432 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 119816 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 205599 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 208450 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2332 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2285 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 60396 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 185275 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 215084 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6734 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1009149 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1184105 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 2602 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 62821096 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1023 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1006 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 122403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 187562 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 168232 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1111 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1082 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 44367 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 119988 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 124913 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6868 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 778555 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 981258 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1186708 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 2355 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1932 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 161630 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::total 1361276 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 161630 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 243103 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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-system.physmem.bytesWritten 115242304 # Total number of bytes written to DRAM
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-system.physmem.mergedWrBursts 49721 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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-system.physmem.totGap 47443137361000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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-system.physmem.bytesPerActivate::mean 176.667963 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 107.708761 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 246.723752 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 648817 63.75% 63.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 197916 19.45% 83.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 48918 4.81% 88.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 23519 2.31% 90.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 17229 1.69% 92.01% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 11413 1.12% 93.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 8164 0.80% 93.93% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7432 0.73% 94.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 54349 5.34% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 1017757 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 78960 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 12.776165 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 140.389446 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 78957 100.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::47 3792 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::49 2703 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 1783 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::54 770 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 913 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 777 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 665 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 582 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 501 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 501 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 424 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 383 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 873 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 836953 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 179.765373 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 108.063876 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 253.948875 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 534704 63.89% 63.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 162086 19.37% 83.25% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 38261 4.57% 87.82% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 18116 2.16% 89.99% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 12763 1.52% 91.51% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 8799 1.05% 92.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 6603 0.79% 93.35% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 6067 0.72% 94.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 49554 5.92% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 836953 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 65558 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 11.869901 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 153.975731 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 65556 100.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::25600-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 78960 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 78960 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 22.804724 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 20.151306 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 21.211366 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 71201 90.17% 90.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 3689 4.67% 94.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 1610 2.04% 96.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 798 1.01% 97.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 435 0.55% 98.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 299 0.38% 98.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 436 0.55% 99.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 198 0.25% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 63 0.08% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 19 0.02% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 61 0.08% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 31 0.04% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 15 0.02% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 6 0.01% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 4 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 5 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 7 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 4 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 9 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 8 0.01% 99.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 9 0.01% 99.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 14 0.02% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 2 0.00% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 5 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 4 0.01% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::416-431 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::432-447 4 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 3 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 3 0.00% 99.98% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 5 0.01% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 3 0.00% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 65558 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 65558 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 23.989475 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 20.876910 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 23.036255 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 57911 88.34% 88.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 3625 5.53% 93.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 1537 2.34% 96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 756 1.15% 97.36% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 457 0.70% 98.06% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 339 0.52% 98.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 446 0.68% 99.26% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 180 0.27% 99.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 59 0.09% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 25 0.04% 99.66% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 57 0.09% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 41 0.06% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 16 0.02% 99.83% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 6 0.01% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 2 0.00% 99.85% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 7 0.01% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 6 0.01% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 4 0.01% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 12 0.02% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 9 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 13 0.02% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 20 0.03% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 3 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::400-415 2 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 2 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::448-463 1 0.00% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 4 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 4 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 4 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::576-591 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::704-719 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::672-687 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 78960 # Writes before turning the bus around for reads
-system.physmem.totQLat 36416381887 # Total ticks spent queuing
-system.physmem.totMemAccLat 55331681887 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 5044080000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 36098.14 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 65558 # Writes before turning the bus around for reads
+system.physmem.totQLat 24526926504 # Total ticks spent queuing
+system.physmem.totMemAccLat 39117801504 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 3890900000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 31518.32 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 54848.14 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.36 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.43 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.36 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.49 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 50268.32 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.05 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.13 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.05 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.19 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.03 # Data bus utilization in percentage
+system.physmem.busUtil 0.02 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
-system.physmem.readRowHits 756126 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1035585 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.95 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 57.51 # Row buffer hit rate for writes
-system.physmem.avgGap 16591131.66 # Average gap between requests
-system.physmem.pageHitRate 63.77 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3944550960 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 2152284750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3829511400 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5947512480 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1192681206900 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27419667632250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31726977439380 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.736993 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45614623336779 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1584230440000 # Time in different power states
+system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 26.72 # Average write queue length when enqueuing
+system.physmem.readRowHits 582169 # Number of row buffer hits during reads
+system.physmem.writeRowHits 931750 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.81 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 59.24 # Row buffer hit rate for writes
+system.physmem.avgGap 19730499.53 # Average gap between requests
+system.physmem.pageHitRate 64.40 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 3287730600 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 1793900625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2969101200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 5201632080 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1175633111385 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27388306372500 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31670904725190 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.643023 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45562569995604 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1581652800000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 244280410221 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 221716854896 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3749639040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 2045934000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 4039144200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5720654160 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3098754740640 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1188668792790 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27423187293750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31726166198580 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.719894 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45620445429017 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1584230440000 # Time in different power states
+system.physmem_1.actEnergy 3039558480 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 1658489250 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3100125600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 4989373200 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3093712876800 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1167524389710 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27395419294500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31669444107540 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.612186 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45574402608448 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1581652800000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 238458431983 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 209885438552 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 704 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 130059643 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 92054393 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 5970282 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 98035548 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 70777475 # Number of BTB hits
+system.cpu0.branchPred.lookups 133649210 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 93568356 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6412350 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 100434532 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 71867706 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.195725 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 15296635 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 1065115 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 71.556769 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 16148203 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 1115497 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 268213 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 268213 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8180 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 73055 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 268213 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 268213 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 268213 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 81235 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 18802.895870 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 17058.372218 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 13418.609606 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 80487 99.08% 99.08% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 639 0.79% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 31 0.04% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 33 0.04% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 28 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 81235 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 281840 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 281840 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8577 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76588 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 281840 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 281840 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 281840 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 85165 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 18850.134868 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17191.967454 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 12262.040349 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 80924 95.02% 95.02% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 3552 4.17% 99.19% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303 385 0.45% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 20 0.02% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607 10 0.01% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375 25 0.03% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143 15 0.02% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.01% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679 16 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 85165 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 788586204 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 788586204 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 788586204 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 73055 89.93% 89.93% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 8180 10.07% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 81235 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 268213 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 76588 89.93% 89.93% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 8577 10.07% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 85165 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 281840 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 268213 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81235 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 281840 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85165 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81235 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 349448 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85165 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 367005 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 82876233 # DTB read hits
-system.cpu0.dtb.read_misses 221834 # DTB read misses
-system.cpu0.dtb.write_hits 73950839 # DTB write hits
-system.cpu0.dtb.write_misses 46379 # DTB write misses
+system.cpu0.dtb.read_hits 86621651 # DTB read hits
+system.cpu0.dtb.read_misses 235326 # DTB read misses
+system.cpu0.dtb.write_hits 77269391 # DTB write hits
+system.cpu0.dtb.write_misses 46514 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 33850 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 2174 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 9634 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 36825 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 2231 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 9213 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10897 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 83098067 # DTB read accesses
-system.cpu0.dtb.write_accesses 73997218 # DTB write accesses
+system.cpu0.dtb.perms_faults 11443 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 86856977 # DTB read accesses
+system.cpu0.dtb.write_accesses 77315905 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 156827072 # DTB hits
-system.cpu0.dtb.misses 268213 # DTB misses
-system.cpu0.dtb.accesses 157095285 # DTB accesses
+system.cpu0.dtb.hits 163891042 # DTB hits
+system.cpu0.dtb.misses 281840 # DTB misses
+system.cpu0.dtb.accesses 164172882 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 59559 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 59559 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 562 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 52025 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 59559 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 59559 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 59559 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 52587 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 21528.762508 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 19318.036298 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 15879.557576 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 47969 91.22% 91.22% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 3703 7.04% 98.26% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 280 0.53% 98.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 523 0.99% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 24 0.05% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 24 0.05% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 16 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 8 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 66347 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 66347 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 679 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58898 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 66347 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 66347 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 66347 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 59577 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 21233.631049 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19420.255520 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 13392.583355 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-32767 54894 92.14% 92.14% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::32768-65535 3878 6.51% 98.65% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-98303 278 0.47% 99.12% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::98304-131071 464 0.78% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.02% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-229375 21 0.04% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::229376-262143 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::425984-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 52587 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 59577 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 787865704 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 787865704 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 787865704 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 52025 98.93% 98.93% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 562 1.07% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 52587 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 58898 98.86% 98.86% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 679 1.14% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 59577 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 59559 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 59559 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 66347 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 66347 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 52587 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 52587 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 112146 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 232580630 # ITB inst hits
-system.cpu0.itb.inst_misses 59559 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59577 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59577 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 125924 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 239632917 # ITB inst hits
+system.cpu0.itb.inst_misses 66347 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 23871 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26379 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 192056 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 196328 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 232640189 # ITB inst accesses
-system.cpu0.itb.hits 232580630 # DTB hits
-system.cpu0.itb.misses 59559 # DTB misses
-system.cpu0.itb.accesses 232640189 # DTB accesses
-system.cpu0.numCycles 928928804 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 239699264 # ITB inst accesses
+system.cpu0.itb.hits 239632917 # DTB hits
+system.cpu0.itb.misses 66347 # DTB misses
+system.cpu0.itb.accesses 239699264 # DTB accesses
+system.cpu0.numCycles 955623985 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 429144762 # Number of instructions committed
-system.cpu0.committedOps 504441860 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 43734034 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 3788 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 93957994041 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.164605 # CPI: cycles per instruction
-system.cpu0.ipc 0.461978 # IPC: instructions per cycle
+system.cpu0.committedInsts 445844997 # Number of instructions committed
+system.cpu0.committedOps 524389125 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 43457031 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 4220 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 93776986984 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.143400 # CPI: cycles per instruction
+system.cpu0.ipc 0.466549 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 12678 # number of quiesce instructions executed
-system.cpu0.tickCycles 694752800 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 234176004 # Total number of cycles that the object has spent stopped
-system.cpu0.dcache.tags.replacements 5394073 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 480.331401 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 148625740 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5394584 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 27.550918 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 5096417500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.331401 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938147 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.938147 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 13187 # number of quiesce instructions executed
+system.cpu0.tickCycles 717454138 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 238169847 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 5506052 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 502.001203 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 155497940 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 5506563 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 28.238656 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 5093256500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 502.001203 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.980471 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.980471 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 354 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 50 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 331 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 25 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 316412315 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 316412315 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 75879605 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 75879605 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 68405292 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 68405292 # number of WriteReq hits
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-system.cpu0.dcache.SoftPFReq_hits::total 266627 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 249000 # number of WriteInvalidateReq hits
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-system.cpu0.dcache.LoadLockedReq_hits::total 1685353 # number of LoadLockedReq hits
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-system.cpu0.dcache.StoreCondReq_hits::total 1648257 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 144284897 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 144284897 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 144551524 # number of overall hits
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-system.cpu0.dcache.ReadReq_misses::total 3254530 # number of ReadReq misses
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-system.cpu0.dcache.WriteReq_misses::total 2315784 # number of WriteReq misses
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-system.cpu0.dcache.SoftPFReq_misses::total 640707 # number of SoftPFReq misses
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-system.cpu0.dcache.WriteInvalidateReq_misses::total 788472 # number of WriteInvalidateReq misses
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-system.cpu0.dcache.LoadLockedReq_misses::total 144645 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 180684 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 180684 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 5570314 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 5570314 # number of demand (read+write) misses
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-system.cpu0.dcache.overall_misses::total 6211021 # number of overall misses
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-system.cpu0.dcache.WriteReq_miss_latency::total 45032988844 # number of WriteReq miss cycles
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-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 32697185728 # number of WriteInvalidateReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2134918217 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 3587000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 3587000 # number of StoreCondFailReq miss cycles
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-system.cpu0.dcache.demand_miss_latency::total 94514045590 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 94514045590 # number of overall miss cycles
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-system.cpu0.dcache.SoftPFReq_accesses::total 907334 # number of SoftPFReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total 1828941 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.overall_accesses::total 150762545 # number of overall (read+write) accesses
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-system.cpu0.dcache.WriteReq_avg_miss_latency::total 19446.109328 # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41469.051188 # average WriteInvalidateReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14759.709751 # average LoadLockedReq miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21298.054604 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 330491760 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 330491760 # Number of data accesses
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14872.076848 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 18814.981471 # average WriteReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 39912.911740 # average WriteInvalidateReq miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 39912.911740 # average WriteInvalidateReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14680.769116 # average LoadLockedReq miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16967.453826 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16967.453826 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15217.151188 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 3714069 # number of writebacks
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-system.cpu0.dcache.ReadReq_mshr_hits::total 414551 # number of ReadReq MSHR hits
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-system.cpu0.dcache.demand_mshr_hits::total 1387642 # number of demand (read+write) MSHR hits
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-system.cpu0.dcache.overall_mshr_hits::total 1387642 # number of overall MSHR hits
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-system.cpu0.dcache.ReadReq_mshr_misses::total 2839979 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1342693 # number of WriteReq MSHR misses
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-system.cpu0.dcache.SoftPFReq_mshr_misses::total 635024 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 788383 # number of WriteInvalidateReq MSHR misses
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104432 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104432 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.StoreCondReq_mshr_misses::total 180642 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 4182672 # number of demand (read+write) MSHR misses
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-system.cpu0.dcache.overall_mshr_misses::total 4817696 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37224821633 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1352929391 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3566593771 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3248500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3248500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61545107041 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 61545107041 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75975107148 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 75975107148 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5918601247 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5918601247 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5692373000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692373000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11610974247 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11610974247 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035888 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035888 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018986 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018986 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.699879 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.699879 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.759908 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.759908 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.057067 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.057067 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098769 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098769 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027911 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.027911 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031956 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.031956 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13107.428482 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13107.428482 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18113.064869 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18113.064869 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22723.550774 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22723.550774 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39961.754657 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 39961.754657 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12955.122865 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12955.122865 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19743.989609 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19743.989609 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 3760610 # number of writebacks
+system.cpu0.dcache.writebacks::total 3760610 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 413115 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 413115 # number of ReadReq MSHR hits
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+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42490 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42490 # number of LoadLockedReq MSHR hits
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+system.cpu0.dcache.StoreCondReq_mshr_hits::total 52 # number of StoreCondReq MSHR hits
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+system.cpu0.dcache.overall_mshr_hits::total 1379824 # number of overall MSHR hits
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+system.cpu0.dcache.WriteReq_mshr_misses::total 1345143 # number of WriteReq MSHR misses
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+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 115009 # number of LoadLockedReq MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23537156289 # number of WriteReq MSHR miss cycles
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+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13208319439 # number of SoftPFReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1454810141 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.overall_mshr_miss_latency::total 74408242859 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5916157251 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5692664250 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11608821501 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035312 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035312 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018170 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018170 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.683798 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.683798 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.762227 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.762227 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064793 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064793 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.103512 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.103512 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027224 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.027224 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.030966 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.030966 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12868.566149 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12868.566149 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17497.884083 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17497.884083 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21477.605713 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21477.605713 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 38406.254280 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 38406.254280 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12649.533002 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12649.533002 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19673.919003 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19673.919003 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14714.303928 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14714.303928 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15770.008558 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15770.008558 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14326.264083 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14326.264083 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15226.217882 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15226.217882 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 177881.393036 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 177881.393036 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 171657.095257 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 171657.095257 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 174773.742149 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174773.742149 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 9298569 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.930207 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 223083541 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 9299081 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 23.989848 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 24039613250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930207 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999864 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999864 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 9994306 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.930109 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 229434949 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 9994818 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 22.955390 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 24035147250 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.930109 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999863 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total 0.999863 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 423 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 35 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 254 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 474064354 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 474064354 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 223083541 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 223083541 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 223083541 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 223083541 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 223083541 # number of overall hits
-system.cpu0.icache.overall_hits::total 223083541 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 9299091 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 9299091 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 9299091 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 9299091 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 9299091 # number of overall misses
-system.cpu0.icache.overall_misses::total 9299091 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 92099739258 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 92099739258 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 92099739258 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 92099739258 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 92099739258 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 92099739258 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 232382632 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 232382632 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 232382632 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 232382632 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 232382632 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 232382632 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.040016 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.040016 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.040016 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.040016 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.040016 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.040016 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9904.165822 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 9904.165822 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 9904.165822 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9904.165822 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 9904.165822 # average overall miss latency
+system.cpu0.icache.tags.tag_accesses 488854379 # Number of tag accesses
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 4833897250 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 4833897250 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 4833897250 # number of overall MSHR uncacheable cycles
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average ReadReq mshr miss latency
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-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8901.210848 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 92413.964670 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.l2cache.prefetcher.pfIdentified 7193896 # number of prefetch candidates identified
-system.cpu0.l2cache.prefetcher.pfBufferHit 3174 # number of redundant prefetches already in prefetch queue
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 922256 # number of prefetches not generated due to page crossing
-system.cpu0.l2cache.tags.replacements 2625541 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 15991.413435 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 14807300 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 2641343 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 5.605974 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 5822698500 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 4879.764539 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 24.400359 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 12.549912 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 6476.155414 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3443.547426 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1154.995785 # Average occupied blocks per requestor
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-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 131 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 212 # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 49 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id
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-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 584 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3987 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7940 # Occupied blocks per task id
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-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5652021253 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10043092003 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443565000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443565000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5650020250 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 10041091000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 5443925500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 5443925500 # number of WriteReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 4391070750 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11095586253 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15486657003 # number of overall MSHR uncacheable cycles
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.264207 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.126293 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses
-system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11093945750 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 15485016500 # number of overall MSHR uncacheable cycles
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.258465 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.122136 # mshr miss rate for ReadReq accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000001 # mshr miss rate for Writeback accesses
+system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000001 # mshr miss rate for Writeback accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.741100 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.741100 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.548089 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.548089 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.823139 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.823139 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.717313 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.717313 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.551302 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.551302 # mshr miss rate for UpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.814827 # mshr miss rate for SCUpgradeReq accesses
+system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.814827 # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231620 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231620 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.134417 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.023192 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.054089 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.079621 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.256397 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.231279 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.231279 # mshr miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for demand accesses
+system.cpu0.l2cache.demand_mshr_miss_rate::total 0.130125 # mshr miss rate for demand accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.021107 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.046455 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.078644 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.252041 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.181983 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27403.946250 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 25858.743437 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 46843.898684 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43693.358009 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43693.358009 # average WriteInvalidateReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20356.764149 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20356.764149 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14871.267151 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14871.267151 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 907166 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 907166 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39927.981557 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39927.981557 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27728.591352 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28990.653748 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 30822.667702 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23784.778281 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30115.739692 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 46843.898684 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 32724.888480 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.174466 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 26070.333025 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24914.421505 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 39284.329024 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 42944.709754 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 42944.709754 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20269.613166 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20269.613166 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14936.844150 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14936.844150 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 441333 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 441333 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37752.863775 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37752.863775 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26584.661076 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 23392.109673 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 25808.496171 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 23536.406368 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28603.508173 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 39284.329024 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 29812.315639 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 169879.438648 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 117349.075567 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164156.605253 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164156.605253 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83948.051886 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 167022.157568 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 130423.203261 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 16236238 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 13810704 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 33172 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 33172 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3714064 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 1025800 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1145042 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 786829 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 475552 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336189 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 478151 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 52 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1267323 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1138296 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18702794 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15835764 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 326673 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1038123 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 35903354 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 598489344 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 596885449 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1190176 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 3791640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1200356609 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 4763261 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 24114639 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.184867 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.388190 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 16764997 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 14635279 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 33163 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3760609 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 997781 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1159753 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 821059 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 475624 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 336764 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 482191 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1257493 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1141567 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 20094267 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16118866 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366766 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1099589 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 37679488 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 643016512 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 607271415 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1349104 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4039944 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1255676975 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 4414025 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 24791334 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.197604 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.398192 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 19656632 81.51% 81.51% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 4458007 18.49% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 19892474 80.24% 80.24% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 4898860 19.76% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 24114639 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 14405309409 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 24791334 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 14940946397 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 207723992 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 210442490 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 14053020534 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 15097277267 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7776245419 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7911607131 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 178137962 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 198319454 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 564500428 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 594828175 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 140284857 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 99939687 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6358953 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 105820632 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 77032296 # Number of BTB hits
+system.cpu1.branchPred.lookups 123549187 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 87841692 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 5708078 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 93157119 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 67436708 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 72.795158 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 16359380 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 1035022 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 72.390289 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 14460012 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 934859 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 298079 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 298079 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11270 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 91179 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 298079 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 298079 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 298079 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 102449 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 19055.295776 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17104.036055 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 15328.339502 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 101103 98.69% 98.69% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1144 1.12% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 36 0.04% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 71 0.07% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 73 0.07% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 15 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 102449 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1267166444 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1267166444 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1267166444 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 91179 89.00% 89.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 11270 11.00% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 102449 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 298079 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 259362 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 259362 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 8416 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 76621 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 259362 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 259362 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 259362 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 85037 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 18225.042946 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 16628.571422 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 11774.469557 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767 81545 95.89% 95.89% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535 2790 3.28% 99.17% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303 403 0.47% 99.65% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071 201 0.24% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839 25 0.03% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607 11 0.01% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375 23 0.03% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143 9 0.01% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911 14 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 85037 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1261494444 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1261494444 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1261494444 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 76621 90.10% 90.10% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 8416 9.90% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 85037 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 259362 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 298079 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 102449 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 259362 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 85037 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 102449 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 400528 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 85037 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 344399 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 91176680 # DTB read hits
-system.cpu1.dtb.read_misses 248433 # DTB read misses
-system.cpu1.dtb.write_hits 79002879 # DTB write hits
-system.cpu1.dtb.write_misses 49646 # DTB write misses
+system.cpu1.dtb.read_hits 80542266 # DTB read hits
+system.cpu1.dtb.read_misses 214982 # DTB read misses
+system.cpu1.dtb.write_hits 69249357 # DTB write hits
+system.cpu1.dtb.write_misses 44380 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 41482 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 884 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 7879 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 38373 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1014 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 35601 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 736 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 6438 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11586 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 91425113 # DTB read accesses
-system.cpu1.dtb.write_accesses 79052525 # DTB write accesses
+system.cpu1.dtb.perms_faults 9960 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 80757248 # DTB read accesses
+system.cpu1.dtb.write_accesses 69293737 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 170179559 # DTB hits
-system.cpu1.dtb.misses 298079 # DTB misses
-system.cpu1.dtb.accesses 170477638 # DTB accesses
+system.cpu1.dtb.hits 149791623 # DTB hits
+system.cpu1.dtb.misses 259362 # DTB misses
+system.cpu1.dtb.accesses 150050985 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 68407 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 68407 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 609 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 58709 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 68407 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 68407 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 68407 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 59318 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21639.401767 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 18915.934077 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 18524.659910 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 54668 92.16% 92.16% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 3100 5.23% 97.39% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 594 1.00% 98.39% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 801 1.35% 99.74% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 32 0.05% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 14 0.02% 99.82% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 58 0.10% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 21 0.04% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 5 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 4 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 10 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 4 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walks 60478 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60478 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 478 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 50972 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60478 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60478 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60478 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 51450 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 20568.513975 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 18499.951285 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 14805.800668 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 47723 92.76% 92.76% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 2940 5.71% 98.47% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 278 0.54% 99.01% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 425 0.83% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 16 0.03% 99.87% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 10 0.02% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 27 0.05% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 13 0.03% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 6 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::360448-393215 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 59318 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1266435944 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1266435944 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1266435944 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 58709 98.97% 98.97% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 609 1.03% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 59318 # Table walker page sizes translated
+system.cpu1.itb.walker.walkCompletionTime::total 51450 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1260837944 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1260837944 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1260837944 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 50972 99.07% 99.07% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 478 0.93% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 51450 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 68407 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 68407 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60478 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60478 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 59318 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 59318 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 127725 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 251160195 # ITB inst hits
-system.cpu1.itb.inst_misses 68407 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 51450 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 51450 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 111928 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 220701471 # ITB inst hits
+system.cpu1.itb.inst_misses 60478 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 41692 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1050 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 30244 # Number of entries that have been flushed from TLB
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system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 224879 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 203408 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
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-system.cpu1.itb.accesses 251228602 # DTB accesses
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+system.cpu1.itb.accesses 220761949 # DTB accesses
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu1.numFetchSuspends 5811 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 93949323576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.031848 # CPI: cycles per instruction
-system.cpu1.ipc 0.492163 # IPC: instructions per cycle
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+system.cpu1.ipc 0.496860 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu1.dcache.tags.total_refs 161882040 # Total number of references to valid blocks.
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-system.cpu1.dcache.tags.avg_refs 29.422287 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8380046591500 # Cycle when the warmup percentage was hit.
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system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 15923.120490 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14320.470435 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 13777.003348 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3514313 # number of writebacks
-system.cpu1.dcache.writebacks::total 3514313 # number of writebacks
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036585 # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.858147 # mshr miss rate for WriteInvalidateReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069518 # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.908562 # average ReadReq mshr miss latency
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+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25528.299140 # average WriteInvalidateReq mshr miss latency
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system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14036.712284 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14036.712284 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14794.275841 # average overall mshr miss latency
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+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13379.618472 # average overall mshr miss latency
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+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 101931.044659 # average ReadReq mshr uncacheable latency
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-system.cpu1.icache.demand_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8935.194612 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 8935.194612 # average overall mshr miss latency
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for demand accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for demand accesses
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-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053767 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.085928 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.245886 # mshr miss rate for overall accesses
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24574.564200 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45129.323351 # average HardPFReq mshr miss latency
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-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32101.818529 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19546.883813 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19546.883813 # average UpgradeReq mshr miss latency
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-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14787.980462 # average SCUpgradeReq mshr miss latency
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 235874.750000 # average SCUpgradeFailReq mshr miss latency
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-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33359.452778 # average ReadExReq mshr miss latency
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-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency
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-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 35517.674447 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22440.200456 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27479.472783 # average overall mshr miss latency
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-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 16743915 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 14472665 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 5158 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 5158 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3514312 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 1035959 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1137929 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 455738 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 448749 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 344575 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 466415 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 78 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1299611 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1147815 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 19064189 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15671741 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 370835 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1205745 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 36312510 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 610054016 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 588145619 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1332264 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4367048 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 1203898947 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4911557 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 24519969 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.188170 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.390848 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 15242466 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 12851003 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 5087 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3038484 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 900400 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1105427 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 417532 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 439071 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 337307 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 446846 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 71 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1140783 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 991898 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17100855 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13710565 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 326713 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1037575 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 32175708 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 547227328 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 511521449 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1168464 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3734152 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 1063651393 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4928167 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 22242259 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 1.242416 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.428544 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 19906035 81.18% 81.18% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 4613934 18.82% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 16850390 75.76% 75.76% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 5391869 24.24% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 24519969 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 13930930666 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 22242259 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 12259577677 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 160378480 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 163507981 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 14310919255 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 12835259097 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8198844119 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7129308669 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 204674963 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 180853196 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 660298903 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 571040175 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40379 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40379 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136954 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29970 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40383 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40383 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136956 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29972 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106984 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47756 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47768 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122846 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122858 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231740 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 231740 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354666 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47776 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 354678 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47788 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155884 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 155896 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7355312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 7355312 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7513282 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36279000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 7513294 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 36287000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 609062244 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 608916622 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92879000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92889000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 148791282 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 148804483 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 171000 # Layer occupancy (ticks)
+system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115866 # number of replacements
-system.iocache.tags.tagsinuse 11.306200 # Cycle average of tags in use
+system.iocache.tags.replacements 115850 # number of replacements
+system.iocache.tags.tagsinuse 11.297267 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115882 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115866 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9129676346000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 7.405197 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 3.901004 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.462825 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.243813 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.706638 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 9129662020000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.840346 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.456922 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.240022 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.466058 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.706079 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses 1043187 # Number of tag accesses
system.iocache.tags.data_accesses 1043187 # Number of data accesses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
system.iocache.overall_misses::realview.ide 8886 # number of overall misses
system.iocache.overall_misses::total 8926 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ethernet 5190000 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1626687073 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1631877073 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ethernet 5219500 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1645546182 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1650765682 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19941362889 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 19941362889 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ethernet 5559000 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1626687073 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1632246073 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ethernet 5559000 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 1626687073 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 1632246073 # number of overall miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19952013957 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 19952013957 # number of WriteInvalidateReq miss cycles
+system.iocache.demand_miss_latency::realview.ethernet 5588500 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1645546182 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1651134682 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ethernet 5588500 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1645546182 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1651134682 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide 8886 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 8923 # number of ReadReq accesses(hits+misses)
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140270.270270 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 183061.790795 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 182884.352012 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ethernet 141067.567568 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 185184.130317 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 185001.197131 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186395.749729 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 186395.749729 # average WriteInvalidateReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ethernet 138975 # average overall miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 182864.225073 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ethernet 138975 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 183061.790795 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 182864.225073 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 111964 # number of cycles access was blocked
+system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186495.307308 # average WriteInvalidateReq miss latency
+system.iocache.WriteInvalidateReq_avg_miss_latency::total 186495.307308 # average WriteInvalidateReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 184980.358727 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ethernet 139712.500000 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 185184.130317 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 184980.358727 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 111929 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 16416 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 16372 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 6.820419 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 6.836611 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks::writebacks 106950 # number of writebacks
-system.iocache.writebacks::total 106950 # number of writebacks
+system.iocache.writebacks::writebacks 106949 # number of writebacks
+system.iocache.writebacks::total 106949 # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide 8886 # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total 8923 # number of ReadReq MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide 8886 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 8926 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3264000 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 1163415573 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 1166679573 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3294500 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 1182279102 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 1185573602 # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14378130953 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14378130953 # number of WriteInvalidateReq MSHR miss cycles
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 74287.640228 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 94467.846634 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 145636.010011 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88614.605858 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138052.535948 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60948.109240 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 147997.090572 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 63611.111111 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81455.350118 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 107392.516300 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 921958 # Transaction distribution
-system.membus.trans_dist::ReadResp 921958 # Transaction distribution
-system.membus.trans_dist::WriteReq 38330 # Transaction distribution
-system.membus.trans_dist::WriteResp 38330 # Transaction distribution
-system.membus.trans_dist::Writeback 1184105 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 663691 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 663691 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 435500 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 292205 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 115129 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 30 # Transaction distribution
-system.membus.trans_dist::ReadExReq 144960 # Transaction distribution
-system.membus.trans_dist::ReadExResp 128452 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122846 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 709274 # Transaction distribution
+system.membus.trans_dist::ReadResp 709274 # Transaction distribution
+system.membus.trans_dist::WriteReq 38250 # Transaction distribution
+system.membus.trans_dist::WriteResp 38250 # Transaction distribution
+system.membus.trans_dist::Writeback 981258 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 638260 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 638259 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 441618 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 290995 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 111840 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 38 # Transaction distribution
+system.membus.trans_dist::ReadExReq 127489 # Transaction distribution
+system.membus.trans_dist::ReadExResp 110378 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122858 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 52 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25278 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5060662 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5208838 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336578 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 336578 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5545416 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155884 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25102 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4347669 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4495681 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 336711 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 336711 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4832392 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155896 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1324 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50556 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168740232 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 168947996 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14122752 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14122752 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 183070748 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 632037 # Total snoops (count)
-system.membus.snoop_fanout::samples 3551920 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50204 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 139364352 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 139571776 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14131264 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14131264 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 153703040 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 640714 # Total snoops (count)
+system.membus.snoop_fanout::samples 3227461 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3551920 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3227461 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3551920 # Request fanout histogram
-system.membus.reqLayer0.occupancy 109974000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3227461 # Request fanout histogram
+system.membus.reqLayer0.occupancy 110051499 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33484 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 21181500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 20984500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 10917620106 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 9462597488 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 6186347625 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 4943193797 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 152234718 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 152223017 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 4966231 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4959010 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38330 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38330 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2396374 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 933256 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 826108 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 485771 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 304174 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 789945 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 119 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 119 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 295867 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 295867 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7796872 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6899953 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 14696825 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 260005833 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 222466259 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 482472092 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1634381 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9291173 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012493 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.111071 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 4701983 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4694752 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38250 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38250 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2214381 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 919435 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 812281 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 489803 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 302708 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 792511 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 125 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 125 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 280473 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 280473 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7857713 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6052239 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 13909952 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 261128039 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 189974361 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 451102400 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1657293 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 8947338 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012974 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.113161 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 9175099 98.75% 98.75% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 116074 1.25% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 8831258 98.70% 98.70% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 116080 1.30% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9291173 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 8184497542 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8947338 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 7728831785 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2554500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2539500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4445775595 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4493592227 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 4394903352 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 3891101888 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 51609998980000 # Number of ticks simulated
final_tick 51609998980000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 125549 # Simulator instruction rate (inst/s)
-host_op_rate 147521 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6837484784 # Simulator tick rate (ticks/s)
-host_mem_usage 653616 # Number of bytes of host memory used
-host_seconds 7548.10 # Real time elapsed on the host
+host_inst_rate 182485 # Simulator instruction rate (inst/s)
+host_op_rate 214421 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 9938249935 # Simulator tick rate (ticks/s)
+host_mem_usage 720032 # Number of bytes of host memory used
+host_seconds 5193.07 # Real time elapsed on the host
sim_insts 947659008 # Number of instructions simulated
sim_ops 1113505098 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 8185275 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9651575 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9651575 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 33696 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 67401 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 84566997800 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 84566997800 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78901247228 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19971.014416 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19292.065367 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 19292.065367 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170695.156458 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170695.156458 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166484.683281 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166484.683281 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168589.638759 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168589.638759 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 24538707 # number of replacements
system.cpu.icache.tags.tagsinuse 511.926996 # Cycle average of tags in use
system.cpu.icache.demand_mshr_misses::total 24539229 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 24539229 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 24539229 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total 52294 # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total 52294 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 290116862082 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 290116862082 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 290116862082 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11822.574462 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11822.574462 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 76950.806976 # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 76950.806976 # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 76950.806976 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1594461 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65370.145273 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 107545 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1025546 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1144509 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 52294 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33696 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 85990 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33705 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33705 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 52294 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67401 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 119695 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 460278992 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 386982750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7477222552 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69526.454526 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70673.372070 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70600.823870 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156677.253977 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 97549.909873 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153464.085447 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153464.085447 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59450.797415 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155070.455186 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 113294.822257 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 33827953 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 33819864 # Transaction distribution
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 7738512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2838692178 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 565529 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 46009467 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.002514 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.050072 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 46129162 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.039419 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.194589 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 45893822 99.75% 99.75% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115645 0.25% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 44310813 96.06% 96.06% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1818349 3.94% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 46009467 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 46129162 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 32777837483 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 1164000 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 14069952 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 212687818 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 2980 # Total snoops (count)
-system.membus.snoop_fanout::samples 3310460 # Request fanout histogram
+system.membus.snoop_fanout::samples 3430156 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3310460 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3430156 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3310460 # Request fanout histogram
+system.membus.snoop_fanout::total 3430156 # Request fanout histogram
system.membus.reqLayer0.occupancy 99903000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 19828 # Layer occupancy (ticks)
sim_ticks 51320468905000 # Number of ticks simulated
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88986 # Simulator instruction rate (inst/s)
-host_op_rate 104557 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5338089020 # Simulator tick rate (ticks/s)
-host_mem_usage 657992 # Number of bytes of host memory used
-host_seconds 9614.02 # Real time elapsed on the host
+host_inst_rate 81731 # Simulator instruction rate (inst/s)
+host_op_rate 96032 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4902851121 # Simulator tick rate (ticks/s)
+host_mem_usage 723872 # Number of bytes of host memory used
+host_seconds 10467.47 # Real time elapsed on the host
sim_insts 855512158 # Number of instructions simulated
sim_ops 1005211605 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 15070815 # number of replacements
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 54956 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 88638 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156696.577642 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.003382 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 34071281 99.66% 99.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 115623 0.34% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3023 # Total snoops (count)
-system.membus.snoop_fanout::samples 2488136 # Request fanout histogram
+system.membus.snoop_fanout::samples 2576774 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2488136 # Request fanout histogram
+system.membus.snoop_fanout::total 2576774 # Request fanout histogram
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
---------- Begin Simulation Statistics ----------
-sim_seconds 47.305566 # Number of seconds simulated
-sim_ticks 47305566199500 # Number of ticks simulated
-final_tick 47305566199500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.385466 # Number of seconds simulated
+sim_ticks 47385466309500 # Number of ticks simulated
+final_tick 47385466309500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 108918 # Simulator instruction rate (inst/s)
-host_op_rate 128082 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5794473291 # Simulator tick rate (ticks/s)
-host_mem_usage 707548 # Number of bytes of host memory used
-host_seconds 8163.91 # Real time elapsed on the host
-sim_insts 889196991 # Number of instructions simulated
-sim_ops 1045647845 # Number of ops (including micro ops) simulated
+host_inst_rate 109383 # Simulator instruction rate (inst/s)
+host_op_rate 128637 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5566054279 # Simulator tick rate (ticks/s)
+host_mem_usage 771804 # Number of bytes of host memory used
+host_seconds 8513.30 # Real time elapsed on the host
+sim_insts 931207580 # Number of instructions simulated
+sim_ops 1095127739 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 75776 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 60928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 4503136 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 12909720 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 13016640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 167424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 164416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 2523040 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 10482528 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 14576384 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 439104 # Number of bytes read from this memory
-system.physmem.bytes_read::total 58919096 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 4503136 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 2523040 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 7026176 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 75116864 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 20812 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 167872 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 148672 # Number of bytes read from this memory
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system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bytesWritten 128743424 # Total number of bytes written to DRAM
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+system.physmem.perBankWrBursts::4 127700 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 81608 # Number of times write queue was full causing retry
-system.physmem.totGap 47305564753000 # Total gap between requests
+system.physmem.numWrRetry 81198 # Number of times write queue was full causing retry
+system.physmem.totGap 47385464863500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 37 # Read request sizes (log2)
+system.physmem.readPktSize::3 25 # Read request sizes (log2)
system.physmem.readPktSize::4 21333 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 915273 # Read request sizes (log2)
+system.physmem.readPktSize::6 1124296 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
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+system.physmem.writePktSize::3 2572 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.wrQLenPdf::63 354953 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 953575 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 182.885667 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 110.719338 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 252.430373 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 592274 62.11% 62.11% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 190618 19.99% 82.10% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 51298 5.38% 87.48% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 22604 2.37% 89.85% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 16941 1.78% 91.63% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 10334 1.08% 92.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 7600 0.80% 93.51% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 7080 0.74% 94.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 54826 5.75% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 953575 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 60764 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 15.409042 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 72.355469 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-511 60757 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::512-1023 4 0.01% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::63 352485 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 1120451 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 180.324302 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 110.099448 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 247.440504 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 698811 62.37% 62.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 221320 19.75% 82.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 61667 5.50% 87.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 27543 2.46% 90.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 21267 1.90% 91.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 12605 1.12% 93.11% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 9064 0.81% 93.92% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 8274 0.74% 94.65% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 59900 5.35% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1120451 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 73379 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 15.608158 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 65.872388 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-511 73373 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::512-1023 3 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-1535 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 60764 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 60764 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 29.435340 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 19.473917 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 995.068690 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-4095 60761 100.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 73379 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 73379 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 27.414056 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 19.095862 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 903.451601 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-4095 73376 100.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::98304-102399 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::102400-106495 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::192512-196607 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 60764 # Writes before turning the bus around for reads
-system.physmem.totQLat 43948740923 # Total ticks spent queuing
-system.physmem.totMemAccLat 61504778423 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 4681610000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 46937.64 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 73379 # Writes before turning the bus around for reads
+system.physmem.totQLat 58866128789 # Total ticks spent queuing
+system.physmem.totMemAccLat 80341216289 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 5726690000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 51396.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 65687.64 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1.27 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.42 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1.25 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.48 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 70146.29 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.55 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.72 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.53 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.58 # Average write queue length when enqueuing
-system.physmem.readRowHits 706637 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1064717 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 75.47 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 59.53 # Row buffer hit rate for writes
-system.physmem.avgGap 17049532.53 # Average gap between requests
-system.physmem.pageHitRate 65.01 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3636465840 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1984182750 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 3644362800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5825759760 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1155369631905 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27369856613250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31630086518865 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.633528 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45532077679143 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1579636760000 # Time in different power states
+system.physmem.avgRdQLen 1.14 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.33 # Average write queue length when enqueuing
+system.physmem.readRowHits 867894 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1168605 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 75.78 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.09 # Row buffer hit rate for writes
+system.physmem.avgGap 14781000.92 # Average gap between requests
+system.physmem.pageHitRate 64.51 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4336385760 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2366083500 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 4510974000 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 6605647200 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1170067048560 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27404900969250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31687774944990 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.723600 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45590272941113 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1582304620000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 193851315857 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 212884395887 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 3572561160 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1949314125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 3658902000 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 5764426560 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3089769502560 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1152447208560 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27372420142500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31629582057465 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.622864 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45536350688414 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1579636760000 # Time in different power states
+system.physmem_1.actEnergy 4134208680 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2255768625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 4422568800 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 6429624480 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3094987836720 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1167604821270 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27407060817750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31686895646325 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.705044 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45593855726560 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1582304620000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 189577142836 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 209300747940 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 384 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 136259129 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 90543195 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 6799058 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 95853282 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 62504832 # Number of BTB hits
+system.cpu0.branchPred.lookups 143219505 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 95215917 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 6874228 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 100849572 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 65904871 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 65.208860 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 18504887 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 186011 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 65.349678 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 19505246 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 190029 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 520196 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 520196 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 10690 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 81668 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 225929 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 294267 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 1575.669375 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 10064.565371 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-65535 292845 99.52% 99.52% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::65536-131071 1067 0.36% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::131072-196607 263 0.09% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::196608-262143 47 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::262144-327679 36 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::327680-393215 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::393216-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 294267 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 252771 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 15945.045037 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 13637.155107 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 11018.196964 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-32767 241135 95.40% 95.40% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-65535 10520 4.16% 99.56% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-98303 548 0.22% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::98304-131071 339 0.13% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::163840-196607 47 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-229375 65 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::229376-262143 16 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-294911 9 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::294912-327679 12 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-360447 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::360448-393215 6 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::458752-491519 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 252771 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 499007353192 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 0.597965 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::stdev 0.527283 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0-1 498187132192 99.84% 99.84% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::2-3 450171500 0.09% 99.93% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::4-5 169118500 0.03% 99.96% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::6-7 80846500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::8-9 62229500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::10-11 34680000 0.01% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::12-13 10096500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::14-15 12800000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::16-17 278500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 499007353192 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 81668 88.43% 88.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 10690 11.57% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 92358 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 520196 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 557114 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 557114 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 11925 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 88835 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 245678 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 311436 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 1783.814331 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 11278.873416 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-65535 309571 99.40% 99.40% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::65536-131071 1396 0.45% 99.85% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::131072-196607 332 0.11% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::196608-262143 57 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::262144-327679 59 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::327680-393215 14 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 311436 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 275434 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 16916.133019 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 14128.427647 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 15086.481481 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-32767 261399 94.90% 94.90% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-65535 11343 4.12% 99.02% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-98303 1146 0.42% 99.44% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::98304-131071 802 0.29% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-163839 102 0.04% 99.77% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::163840-196607 163 0.06% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-229375 287 0.10% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::229376-262143 70 0.03% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-294911 43 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::294912-327679 36 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-360447 22 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::360448-393215 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-425983 9 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::425984-458751 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 275434 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 527372589640 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 0.581951 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::stdev 0.533395 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0-1 526425698140 99.82% 99.82% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::2-3 513345500 0.10% 99.92% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::4-5 204440500 0.04% 99.96% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::6-7 94120000 0.02% 99.97% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::8-9 67519500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::10-11 37561500 0.01% 99.99% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::12-13 13535000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::14-15 16113500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::16-17 245000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::18-19 11000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 527372589640 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 88835 88.16% 88.16% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 11925 11.84% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 100760 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 557114 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 520196 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 92358 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 557114 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 100760 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 92358 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 612554 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 100760 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 657874 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 98496070 # DTB read hits
-system.cpu0.dtb.read_misses 369414 # DTB read misses
-system.cpu0.dtb.write_hits 81551465 # DTB write hits
-system.cpu0.dtb.write_misses 150782 # DTB write misses
+system.cpu0.dtb.read_hits 103903304 # DTB read hits
+system.cpu0.dtb.read_misses 386941 # DTB read misses
+system.cpu0.dtb.write_hits 87265042 # DTB write hits
+system.cpu0.dtb.write_misses 170173 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 36102 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 400 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 5365 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 37535 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 216 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 6819 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 40284 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 98865484 # DTB read accesses
-system.cpu0.dtb.write_accesses 81702247 # DTB write accesses
+system.cpu0.dtb.perms_faults 40407 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 104290245 # DTB read accesses
+system.cpu0.dtb.write_accesses 87435215 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 180047535 # DTB hits
-system.cpu0.dtb.misses 520196 # DTB misses
-system.cpu0.dtb.accesses 180567731 # DTB accesses
+system.cpu0.dtb.hits 191168346 # DTB hits
+system.cpu0.dtb.misses 557114 # DTB misses
+system.cpu0.dtb.accesses 191725460 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 81590 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 81590 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 901 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 59909 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksSquashedBefore 9188 # Table walks squashed before starting
-system.cpu0.itb.walker.walkWaitTime::samples 72402 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::mean 845.170023 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::stdev 6470.995618 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0-32767 72024 99.48% 99.48% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::32768-65535 242 0.33% 99.81% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::65536-98303 56 0.08% 99.89% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::98304-131071 61 0.08% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::131072-163839 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::163840-196607 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::229376-262143 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walks 85759 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 85759 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 908 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 62470 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksSquashedBefore 9907 # Table walks squashed before starting
+system.cpu0.itb.walker.walkWaitTime::samples 75852 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::mean 1136.575173 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::stdev 8938.964276 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0-32767 75266 99.23% 99.23% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::32768-65535 257 0.34% 99.57% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::65536-98303 133 0.18% 99.74% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::98304-131071 159 0.21% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::131072-163839 9 0.01% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::163840-196607 8 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::196608-229375 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::229376-262143 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::294912-327679 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::327680-360447 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::360448-393215 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 72402 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 69998 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 20035.793294 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 17827.568317 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 13688.582598 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-65535 69301 99.00% 99.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-131071 578 0.83% 99.83% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-196607 67 0.10% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-262143 29 0.04% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-393215 7 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkWaitTime::425984-458751 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 75852 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 73285 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 21415.899529 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 18467.660437 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 19009.032462 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 71796 97.97% 97.97% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 1220 1.66% 99.63% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 122 0.17% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 69 0.09% 99.89% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 44 0.06% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 69998 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walksPending::samples 370135740312 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 0.825869 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::stdev 0.379347 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 64468447528 17.42% 17.42% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 305652352784 82.58% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::2 13699000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::3 1205500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::4 35500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 370135740312 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 59909 98.52% 98.52% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 901 1.48% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 60810 # Table walker page sizes translated
+system.cpu0.itb.walker.walkCompletionTime::total 73285 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walksPending::samples 394225556964 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 0.858766 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::stdev 0.348387 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 55694159292 14.13% 14.13% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 338516533172 85.87% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::2 13791500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::3 1055500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::4 17500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 394225556964 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 62470 98.57% 98.57% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 908 1.43% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 63378 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 81590 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 81590 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 85759 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 85759 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 60810 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 60810 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 142400 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 213929001 # ITB inst hits
-system.cpu0.itb.inst_misses 81590 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 63378 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 63378 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 149137 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 225166936 # ITB inst hits
+system.cpu0.itb.inst_misses 85759 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 25953 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 26709 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 203878 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 217420 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 214010591 # ITB inst accesses
-system.cpu0.itb.hits 213929001 # DTB hits
-system.cpu0.itb.misses 81590 # DTB misses
-system.cpu0.itb.accesses 214010591 # DTB accesses
-system.cpu0.numCycles 728554790 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 225252695 # ITB inst accesses
+system.cpu0.itb.hits 225166936 # DTB hits
+system.cpu0.itb.misses 85759 # DTB misses
+system.cpu0.itb.accesses 225252695 # DTB accesses
+system.cpu0.numCycles 777590959 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 88185009 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 601844339 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 136259129 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 81009719 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 601618645 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 14617520 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 1590376 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 274448 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 5655980 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 730298 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 721373 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 213725526 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 1720356 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 27419 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 706084889 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.998504 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.224315 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 90148881 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 632830647 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 143219505 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 85410117 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 647310508 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 14846236 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 1771940 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 282653 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 6199385 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 737729 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 721364 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 224948990 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 1718929 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 28705 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 754595578 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.984480 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.221164 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 368651970 52.21% 52.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 130906496 18.54% 70.75% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 45457211 6.44% 77.19% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 161069212 22.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 398817072 52.85% 52.85% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 138444624 18.35% 71.20% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 47562041 6.30% 77.50% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 169771841 22.50% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 706084889 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.187027 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.826080 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 103877352 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 333585554 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 228251571 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 35190646 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 5179766 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 19720762 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 2170804 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 623516514 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 23718954 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 5179766 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 138234059 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 46790455 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 227164838 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 228535971 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 60179800 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 606373965 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 6065859 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 8641063 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 231610 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 454065 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 27284745 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.FullRegisterEvents 11061 # Number of times there has been no free registers
-system.cpu0.rename.RenamedOperands 577786095 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 931076470 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 716156173 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 752358 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 519674265 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 58111818 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 14452887 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 12546195 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 71496186 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 99205558 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 84922074 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 8773729 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 7651066 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 585335843 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 14506928 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 587846614 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 2739409 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 54557687 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 35502721 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 263475 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 706084889 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.832544 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.074450 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 754595578 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.184184 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.813835 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 107688832 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 365256192 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 237731032 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 38638584 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 5280938 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 20683549 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 2184734 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 657953246 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 23988018 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 5280938 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 144086550 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 51798126 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 247348242 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 239349699 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 66732023 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 640403541 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 6134927 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 9593053 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 279391 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 288384 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 30790790 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.FullRegisterEvents 11378 # Number of times there has been no free registers
+system.cpu0.rename.RenamedOperands 609803525 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 987601051 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 757009838 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 819226 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 550929032 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 58874487 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 16040201 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 14019715 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 78263207 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 104115554 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 90761559 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 9526213 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 8179417 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 617656959 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 16134834 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 622248752 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 2762846 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 55648828 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 35830856 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 282296 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 754595578 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.824612 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.071196 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 387752647 54.92% 54.92% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 129908491 18.40% 73.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 115071565 16.30% 89.61% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 65618038 9.29% 98.90% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 7729861 1.09% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 4287 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 416444489 55.19% 55.19% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 139981431 18.55% 73.74% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 120577545 15.98% 89.72% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 69261363 9.18% 98.90% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 8325608 1.10% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 5142 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 706084889 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 754595578 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 62081849 46.00% 46.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 53806 0.04% 46.04% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 26012 0.02% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 10 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 46.06% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 34882864 25.85% 71.91% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 37902238 28.09% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 64632492 45.32% 45.32% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 49764 0.03% 45.35% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 24321 0.02% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 8 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.37% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 36912792 25.88% 71.25% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 41006253 28.75% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu0.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 401971331 68.38% 68.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 1424969 0.24% 68.62% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntDiv 76351 0.01% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 44028 0.01% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.64% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 101506921 17.27% 85.91% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 82822965 14.09% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
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+system.cpu0.iq.FU_type_0::IntDiv 72707 0.01% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.56% # Type of FU issued
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+system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.56% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 68.56% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.56% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.56% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.56% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 80017 0.01% 68.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.57% # Type of FU issued
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+system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.57% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 106973715 17.19% 85.76% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 88593239 14.24% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 587846614 # Type of FU issued
-system.cpu0.iq.rate 0.806867 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 134946779 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.229561 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 2018256641 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 654059965 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 571438682 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 1207660 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 478909 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 443638 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 722040340 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 753051 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 2688850 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 622248752 # Type of FU issued
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+system.cpu0.iq.fu_busy_rate 0.229210 # FU busy rate (busy events/executed inst)
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+system.cpu0.iq.fp_inst_queue_reads 1361144 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 552290 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 506244 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 764032585 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 841796 # Number of floating point alu accesses
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system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 12347690 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 15246 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 139538 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 5796061 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 12594321 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 16775 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 157768 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 6060902 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 2638151 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 4049170 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 2889033 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 4437246 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 5179766 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 6081153 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 2925805 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 599957845 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 5280938 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 6404578 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 3121375 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 633914393 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 99205558 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 84922074 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 12284210 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 51884 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2819346 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 139538 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 2067264 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 2909526 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 4976790 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 580052597 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 98485742 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 7283117 # Number of squashed instructions skipped in execute
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+system.cpu0.iew.iewIQFullEvents 66239 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2987519 # Number of times the LSQ has become full, causing a stall
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system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 115074 # number of nop insts executed
-system.cpu0.iew.exec_refs 180036231 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 109604684 # Number of branches executed
-system.cpu0.iew.exec_stores 81550489 # Number of stores executed
-system.cpu0.iew.exec_rate 0.796169 # Inst execution rate
-system.cpu0.iew.wb_sent 572646335 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 571882320 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 278067639 # num instructions producing a value
-system.cpu0.iew.wb_consumers 456095391 # num instructions consuming a value
+system.cpu0.iew.exec_nop 122600 # number of nop insts executed
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+system.cpu0.iew.exec_stores 87267333 # Number of stores executed
+system.cpu0.iew.exec_rate 0.790014 # Inst execution rate
+system.cpu0.iew.wb_sent 606266119 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 605472936 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 293481694 # num instructions producing a value
+system.cpu0.iew.wb_consumers 481488998 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.784954 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.609670 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.778652 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.609529 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 47584416 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 14243453 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 4670064 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 697066716 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.782257 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.580851 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 48614829 # The number of squashed insts skipped by commit
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+system.cpu0.commit.branchMispredicts 4732048 # The number of times a branch was mispredicted
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+system.cpu0.commit.committed_per_cycle::mean 0.775637 # Number of insts commited each cycle
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system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 460295975 66.03% 66.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 120461861 17.28% 83.31% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 53495228 7.67% 90.99% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 18161397 2.61% 93.59% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 13064824 1.87% 95.47% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 8746806 1.25% 96.72% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 5864289 0.84% 97.56% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 3641188 0.52% 98.09% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 13335148 1.91% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 493396348 66.19% 66.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 129662648 17.40% 83.59% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 56044004 7.52% 91.11% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 18992920 2.55% 93.66% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 13761945 1.85% 95.50% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 9179296 1.23% 96.73% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 6220016 0.83% 97.57% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 3818014 0.51% 98.08% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 14302886 1.92% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 697066716 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 464477894 # Number of instructions committed
-system.cpu0.commit.committedOps 545285068 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 745378077 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 491403423 # Number of instructions committed
+system.cpu0.commit.committedOps 578142958 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 165983876 # Number of memory references committed
-system.cpu0.commit.loads 86857868 # Number of loads committed
-system.cpu0.commit.membars 3594521 # Number of memory barriers committed
-system.cpu0.commit.branches 103961213 # Number of branches committed
-system.cpu0.commit.fp_insts 434735 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 500421802 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 13758946 # Number of function calls committed.
+system.cpu0.commit.refs 176221889 # Number of memory references committed
+system.cpu0.commit.loads 91521232 # Number of loads committed
+system.cpu0.commit.membars 3904419 # Number of memory barriers committed
+system.cpu0.commit.branches 110044339 # Number of branches committed
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+system.cpu0.commit.int_insts 530522943 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 14584303 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
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-system.cpu0.commit.op_class_0::IntMult 1169798 0.21% 69.54% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntDiv 60419 0.01% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAdd 8 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCmp 13 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatCvt 21 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.55% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 38309 0.01% 69.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.56% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 86857868 15.93% 85.49% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 79126008 14.51% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 400598379 69.29% 69.29% # Class of committed instruction
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+system.cpu0.commit.op_class_0::IntDiv 57671 0.01% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.51% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.51% # Class of committed instruction
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-system.cpu0.committedOps 545285068 # Number of Ops (including micro ops) Simulated
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-system.cpu0.cpi_total 1.568546 # CPI: Total CPI of All Threads
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-system.cpu0.ipc_total 0.637533 # IPC: Total IPC of All Threads
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+system.cpu0.dcache.demand_miss_rate::total 0.083354 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.087140 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.087140 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14956.564020 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14956.564020 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18220.671779 # average WriteReq miss latency
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+system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 46677.544896 # average WriteInvalidateReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14622.637857 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14622.637857 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21102.067618 # average StoreCondReq miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15989.024171 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15989.024171 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15234.028736 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 15234.028736 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 10974284 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 17020056 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 751732 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 670987 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.598665 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 25.365702 # average number of cycles each access was blocked
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+system.cpu0.dcache.avg_blocked_cycles::no_targets 27.133623 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 3967066 # number of writebacks
-system.cpu0.dcache.writebacks::total 3967066 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3312893 # number of ReadReq MSHR hits
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-system.cpu0.dcache.WriteInvalidateReq_mshr_hits::total 4546 # number of WriteInvalidateReq MSHR hits
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-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 123358 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.760215 # mshr miss rate for WriteInvalidateReq accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13160.201648 # average ReadReq mshr miss latency
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22122.912361 # average SoftPFReq mshr miss latency
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-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 44004.150587 # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 12616.227468 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12616.227468 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19701.341183 # average StoreCondReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22705.805221 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 45209.179674 # average WriteInvalidateReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13142.309833 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13142.309833 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19556.206612 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14844.444106 # average overall mshr miss latency
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+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 29450.316582 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 27776.376553 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 61570.737006 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 48815.140097 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 48815.140097 # average WriteInvalidateReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20109.679205 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20109.679205 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14820.003343 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14820.003343 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 473999.800000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 473999.800000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41416.056756 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41416.056756 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 29645.931619 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 33663.134117 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 37840.965556 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24750.114272 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 31902.456753 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 61570.737006 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38609.808035 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 168798.084490 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133312.993536 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162456.957022 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 162456.957022 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80375.316991 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 165657.138071 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 144099.788853 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 13109671 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 10998966 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 32265 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 32265 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3967064 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 987402 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFResp 4 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1170476 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 822992 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 487373 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355558 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 509064 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 118 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1297704 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1174184 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12186882 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16978089 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 390292 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1142423 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 30697686 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 388957536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 639747662 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1404248 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4100656 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1034210102 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 4435865 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 21321710 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.191876 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.393776 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 13667246 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 11407678 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 4196361 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 1120333 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFResp 10 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1176973 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 800387 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 496358 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 355576 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 523512 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1407436 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1277584 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12409061 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 17898439 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 414925 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1222034 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 31944459 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 396067296 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 675577736 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1519008 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 4432728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 1077596768 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 4739028 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 22459193 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.235945 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.424588 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 17230589 80.81% 80.81% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 4091121 19.19% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 17160060 76.41% 76.41% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 5299133 23.59% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 21321710 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 13464993223 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 22459193 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 14039414488 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 208995484 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 204401970 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 9149850308 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 9316604024 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 8376078494 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8912883405 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 215375806 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 225880552 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 630757127 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 669143268 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.branchPred.lookups 124182653 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 82299269 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 6251064 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 87493813 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 57426824 # Number of BTB hits
+system.cpu1.branchPred.lookups 128543512 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 85865577 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 6421624 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 90850028 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 59627534 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 65.635297 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 17076023 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 176220 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 65.632929 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 17292026 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 181846 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 534049 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 534049 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11595 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 85531 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 242787 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 291262 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 2048.229773 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 11850.953616 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-65535 289126 99.27% 99.27% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::65536-131071 1672 0.57% 99.84% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::131072-196607 329 0.11% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::196608-262143 62 0.02% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::262144-327679 62 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::327680-393215 10 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 291262 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 270383 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 17183.802917 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 14328.415565 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 16454.576356 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 267229 98.83% 98.83% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2235 0.83% 99.66% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 352 0.13% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 368 0.14% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 149 0.06% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 35 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::458752-524287 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 270383 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 438879688048 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.596096 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.540539 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0-1 437883178548 99.77% 99.77% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::2-3 543837500 0.12% 99.90% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::4-5 218551000 0.05% 99.95% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::6-7 91365500 0.02% 99.97% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::8-9 75836500 0.02% 99.98% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::10-11 38561500 0.01% 99.99% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::12-13 12555000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::14-15 15271000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::16-17 530000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 438879688048 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 85532 88.06% 88.06% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 11595 11.94% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 97127 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 534049 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 599268 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 599268 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 13824 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 99235 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 280644 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 318624 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 1973.247464 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 12034.928654 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-65535 316338 99.28% 99.28% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::65536-131071 1742 0.55% 99.83% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::131072-196607 377 0.12% 99.95% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::196608-262143 71 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::262144-327679 83 0.03% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::327680-393215 7 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 318624 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 319817 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 17305.058052 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 14691.969456 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 15678.724582 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 316762 99.04% 99.04% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 2191 0.69% 99.73% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 345 0.11% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 267 0.08% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 157 0.05% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 61 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 16 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 8 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 319817 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 467242764496 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.609754 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.540089 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0-1 466086530996 99.75% 99.75% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::2-3 677505500 0.15% 99.90% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::4-5 222526000 0.05% 99.95% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::6-7 100711000 0.02% 99.97% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::8-9 81855500 0.02% 99.98% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::10-11 40422000 0.01% 99.99% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::12-13 15395000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::14-15 17231500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::16-17 579500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::18-19 7500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 467242764496 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 99236 87.77% 87.77% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 13824 12.23% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 113060 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 599268 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 534049 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 97127 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 599268 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 113060 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 97127 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 631176 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 113060 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 712328 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 91849877 # DTB read hits
-system.cpu1.dtb.read_misses 382442 # DTB read misses
-system.cpu1.dtb.write_hits 75119650 # DTB write hits
-system.cpu1.dtb.write_misses 151607 # DTB write misses
+system.cpu1.dtb.read_hits 95146273 # DTB read hits
+system.cpu1.dtb.read_misses 436726 # DTB read misses
+system.cpu1.dtb.write_hits 76756681 # DTB write hits
+system.cpu1.dtb.write_misses 162542 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 39274 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 401 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 5573 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 41064 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 604 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 6738 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 36948 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 92232319 # DTB read accesses
-system.cpu1.dtb.write_accesses 75271257 # DTB write accesses
+system.cpu1.dtb.perms_faults 39860 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 95582999 # DTB read accesses
+system.cpu1.dtb.write_accesses 76919223 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 166969527 # DTB hits
-system.cpu1.dtb.misses 534049 # DTB misses
-system.cpu1.dtb.accesses 167503576 # DTB accesses
+system.cpu1.dtb.hits 171902954 # DTB hits
+system.cpu1.dtb.misses 599268 # DTB misses
+system.cpu1.dtb.accesses 172502222 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 85651 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 85651 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 898 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61483 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksSquashedBefore 9913 # Table walks squashed before starting
-system.cpu1.itb.walker.walkWaitTime::samples 75738 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::mean 1212.145818 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::stdev 8774.873802 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0-32767 75006 99.03% 99.03% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::32768-65535 365 0.48% 99.52% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::65536-98303 180 0.24% 99.75% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::98304-131071 161 0.21% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::131072-163839 8 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::163840-196607 5 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::196608-229375 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walks 83675 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 83675 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 922 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60249 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksSquashedBefore 9641 # Table walks squashed before starting
+system.cpu1.itb.walker.walkWaitTime::samples 74034 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::mean 1137.571926 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::stdev 8570.962609 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0-32767 73376 99.11% 99.11% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::32768-65535 334 0.45% 99.56% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::65536-98303 142 0.19% 99.75% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::98304-131071 157 0.21% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::131072-163839 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::229376-262143 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::294912-327679 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::327680-360447 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::262144-294911 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::294912-327679 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::327680-360447 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::360448-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::425984-458751 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 75738 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 72294 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21947.554182 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 18825.235250 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 19960.579515 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-65535 70492 97.51% 97.51% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-131071 1482 2.05% 99.56% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-196607 157 0.22% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-262143 99 0.14% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 72294 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 404519897680 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::mean 0.847972 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::stdev 0.359205 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 61519279012 15.21% 15.21% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::1 342981503668 84.79% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::2 17484500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::3 1520000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::4 101500 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::5 9000 0.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 404519897680 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 61483 98.56% 98.56% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 898 1.44% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 62381 # Table walker page sizes translated
+system.cpu1.itb.walker.walkWaitTime::total 74034 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 70812 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21947.603838 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 18689.139556 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 20589.258424 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 68933 97.35% 97.35% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 1547 2.18% 99.53% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 153 0.22% 99.75% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 111 0.16% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.05% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 70812 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 419972060240 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::mean 0.852209 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::stdev 0.355033 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 62087724216 14.78% 14.78% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::1 357865938524 85.21% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::2 17105000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::3 1290000 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::4 2500 0.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 419972060240 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 60249 98.49% 98.49% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 922 1.51% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 61171 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 85651 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 85651 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 83675 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 83675 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62381 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62381 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 148032 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 196330607 # ITB inst hits
-system.cpu1.itb.inst_misses 85651 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61171 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61171 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 144846 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 203060553 # ITB inst hits
+system.cpu1.itb.inst_misses 83675 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 41508 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1039 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 28544 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 44809 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1073 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 29792 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 219679 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 217868 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 196416258 # ITB inst accesses
-system.cpu1.itb.hits 196330607 # DTB hits
-system.cpu1.itb.misses 85651 # DTB misses
-system.cpu1.itb.accesses 196416258 # DTB accesses
-system.cpu1.numCycles 659201565 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 203144228 # ITB inst accesses
+system.cpu1.itb.hits 203060553 # DTB hits
+system.cpu1.itb.misses 83675 # DTB misses
+system.cpu1.itb.accesses 203144228 # DTB accesses
+system.cpu1.numCycles 689224896 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 81623724 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 551229784 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 124182653 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 74502847 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 545141022 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 13475474 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 1814701 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 236397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 6195125 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 729177 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 658891 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 196089515 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 1603144 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 28612 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 643136774 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.007577 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.226676 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 83111859 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 570743281 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 128543512 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 76919560 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 571668142 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 13828506 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 1777982 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 253475 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 6260799 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 781198 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 699050 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 202821648 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 1630400 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 27635 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 671466758 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.996773 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.223843 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 333162826 51.80% 51.80% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 120232758 18.69% 70.50% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 41446819 6.44% 76.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 148294371 23.06% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 351036099 52.28% 52.28% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 124470987 18.54% 70.82% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 43050208 6.41% 77.23% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 152909464 22.77% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 643136774 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.188383 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.836208 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 97937463 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 300403958 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 205522733 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 34511986 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 4760634 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 17730932 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 2017504 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 571814983 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 21511068 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 4760634 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 130465176 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 39849524 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 206232237 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 207101717 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 54727486 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 556322152 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 5380569 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 8461915 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 304416 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 605845 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 22227660 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.FullRegisterEvents 11247 # Number of times there has been no free registers
-system.cpu1.rename.RenamedOperands 528347539 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 856455710 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 657084844 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 755426 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 475426080 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 52921453 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 14732861 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 12829203 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 69624573 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 92331469 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 78236769 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 8977003 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 7612209 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 535459998 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 14979383 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 539826932 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 2475624 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 50076597 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 32301398 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 273094 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 643136774 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.839366 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.069808 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 671466758 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.186504 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.828094 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 100354838 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 318587695 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 211284340 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 36331371 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 4908514 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 18177231 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 2045887 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 591006296 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 22089664 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 4908514 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 134210773 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 44178364 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 216212349 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 213325919 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 58630839 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 574898328 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 5600894 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 8989963 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 383271 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 860464 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 24265786 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.FullRegisterEvents 10988 # Number of times there has been no free registers
+system.cpu1.rename.RenamedOperands 548407946 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 889065279 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 679031773 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 678204 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 493384651 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 55023295 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 15514043 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 13585261 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 73076002 # count of insts added to the skid buffer
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+system.cpu1.memDep0.insertedStores 79961275 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 8917606 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 7761424 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 553073173 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 15730545 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 557717167 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 2597694 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 51818937 # Number of squashed instructions iterated over during squash; mainly for profiling
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+system.cpu1.iq.issued_per_cycle::mean 0.830595 # Number of insts issued each cycle
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system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 347132433 53.97% 53.97% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 125915806 19.58% 73.55% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 103467009 16.09% 89.64% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 59513725 9.25% 98.89% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 7103072 1.10% 100.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 4729 0.00% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 364901654 54.34% 54.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 131371089 19.56% 73.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 106572496 15.87% 89.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 61289322 9.13% 98.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 7327865 1.09% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 4332 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 643136774 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 671466758 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 53820631 43.79% 43.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 63940 0.05% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 7561 0.01% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 17 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.85% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 33515144 27.27% 71.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 35487446 28.88% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 55930906 44.08% 44.08% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 67479 0.05% 44.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 9405 0.01% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 14 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.14% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 34760931 27.40% 71.54% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 36114343 28.46% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu1.iq.FU_type_0::No_OpClass 11 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 367420702 68.06% 68.06% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 1281309 0.24% 68.30% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 73255 0.01% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 4 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 2 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.31% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 83298 0.02% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.33% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 94677124 17.54% 85.87% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 76291227 14.13% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::No_OpClass 41 0.00% 0.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 380161908 68.16% 68.16% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 1344725 0.24% 68.41% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 78828 0.01% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 3 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 5 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.42% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 45642 0.01% 68.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 98115732 17.59% 86.02% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 77970283 13.98% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 539826932 # Type of FU issued
-system.cpu1.iq.rate 0.818910 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 122894739 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.227656 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 1846883379 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 600138356 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 524462260 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 1277620 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 518844 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 476158 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 661932910 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 788750 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 2478321 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 557717167 # Type of FU issued
+system.cpu1.iq.rate 0.809195 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 126883078 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.227504 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 1915274546 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 620324151 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 541832642 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 1107318 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 438573 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 407875 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 683910466 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 689738 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 2496582 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 11570290 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 16551 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 142141 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 5437069 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 11949439 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 17528 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 140940 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 5567236 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 2465198 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 3688063 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 2504839 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 3936319 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 4760634 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 6603988 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 1453249 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 550562460 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 4908514 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 7583348 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 1594599 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 568926208 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 92331469 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 78236769 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 12610859 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 52882 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 1339609 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 142141 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 1900150 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 2649580 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 4549730 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 532747017 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 91844367 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 6553150 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 95606432 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 79961275 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 13359998 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 58436 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 1466228 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 140940 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 1941130 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 2763310 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 4704440 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 550354066 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 95142052 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 6771828 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 123079 # number of nop insts executed
-system.cpu1.iew.exec_refs 166962398 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 99765376 # Number of branches executed
-system.cpu1.iew.exec_stores 75118031 # Number of stores executed
-system.cpu1.iew.exec_rate 0.808170 # Inst execution rate
-system.cpu1.iew.wb_sent 525632708 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 524938418 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 254712512 # num instructions producing a value
-system.cpu1.iew.wb_consumers 416314102 # num instructions consuming a value
+system.cpu1.iew.exec_nop 122490 # number of nop insts executed
+system.cpu1.iew.exec_refs 171896040 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 103292614 # Number of branches executed
+system.cpu1.iew.exec_stores 76753988 # Number of stores executed
+system.cpu1.iew.exec_rate 0.798512 # Inst execution rate
+system.cpu1.iew.wb_sent 542951378 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 542240517 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 263529127 # num instructions producing a value
+system.cpu1.iew.wb_consumers 431811268 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.796325 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.611828 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.786740 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.610288 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 43862550 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 14706289 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 4273961 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 634802902 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.788218 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.581621 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 45371481 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 15457669 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 4415885 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 662874998 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.779913 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.574524 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 414870625 65.35% 65.35% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 114759147 18.08% 83.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 48245889 7.60% 91.03% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 16373665 2.58% 93.61% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 11678245 1.84% 95.45% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 7925650 1.25% 96.70% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 5354812 0.84% 97.54% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 3238197 0.51% 98.05% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 12356672 1.95% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 435019222 65.63% 65.63% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 119535237 18.03% 83.66% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 49733246 7.50% 91.16% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 16752738 2.53% 93.69% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 12005106 1.81% 95.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 8186664 1.24% 96.74% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 5495672 0.83% 97.56% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 3379842 0.51% 98.07% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 12767271 1.93% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 634802902 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 424719097 # Number of instructions committed
-system.cpu1.commit.committedOps 500362777 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 662874998 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 439804157 # Number of instructions committed
+system.cpu1.commit.committedOps 516984781 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 153560878 # Number of memory references committed
-system.cpu1.commit.loads 80761178 # Number of loads committed
-system.cpu1.commit.membars 3652883 # Number of memory barriers committed
-system.cpu1.commit.branches 94624372 # Number of branches committed
-system.cpu1.commit.fp_insts 463166 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 459868567 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 12685398 # Number of function calls committed.
+system.cpu1.commit.refs 158051032 # Number of memory references committed
+system.cpu1.commit.loads 83656993 # Number of loads committed
+system.cpu1.commit.membars 3709079 # Number of memory barriers committed
+system.cpu1.commit.branches 98009532 # Number of branches committed
+system.cpu1.commit.fp_insts 399401 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 474457036 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 12875376 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 345616008 69.07% 69.07% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 1054252 0.21% 69.28% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntDiv 58059 0.01% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.30% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 73580 0.01% 69.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.31% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 80761178 16.14% 85.45% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 72799700 14.55% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 357731742 69.20% 69.20% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 1099808 0.21% 69.41% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntDiv 62550 0.01% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.42% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 39649 0.01% 69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.43% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 83656993 16.18% 85.61% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 74394039 14.39% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 500362777 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 12356672 # number cycles where commit BW limit reached
-system.cpu1.rob.rob_reads 1162834468 # The number of ROB reads
-system.cpu1.rob.rob_writes 1096743807 # The number of ROB writes
-system.cpu1.timesIdled 924876 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 16064791 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 93951930875 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 424719097 # Number of Instructions Simulated
-system.cpu1.committedOps 500362777 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.552088 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.552088 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.644293 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.644293 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 629086185 # number of integer regfile reads
-system.cpu1.int_regfile_writes 373708704 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 742781 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 462024 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 113147370 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 113825607 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 2613251902 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 14637394 # number of misc regfile writes
-system.cpu1.dcache.tags.replacements 5151228 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 427.693854 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 143143391 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5151740 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 27.785445 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8478589557500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 427.693854 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.835340 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.835340 # Average percentage of cache occupancy
+system.cpu1.commit.op_class_0::total 516984781 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 12767271 # number cycles where commit BW limit reached
+system.cpu1.rob.rob_reads 1208536006 # The number of ROB reads
+system.cpu1.rob.rob_writes 1133266670 # The number of ROB writes
+system.cpu1.timesIdled 962801 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 17758138 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 94081707774 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 439804157 # Number of Instructions Simulated
+system.cpu1.committedOps 516984781 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.567118 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.567118 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.638114 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.638114 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 649922276 # number of integer regfile reads
+system.cpu1.int_regfile_writes 385926927 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 666608 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 325148 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 119080359 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 119756232 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 2706897787 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 15455536 # number of misc regfile writes
+system.cpu1.dcache.tags.replacements 5466279 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 430.006906 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 146874051 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5466791 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 26.866593 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8478589492000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 430.006906 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.839857 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.839857 # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 394 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 10 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 318663535 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 318663535 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 75155961 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 75155961 # number of ReadReq hits
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-system.cpu1.dcache.WriteReq_hits::total 63737585 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 169811 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 169811 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 58007 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 58007 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1657429 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1657429 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1683439 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1683439 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 138893546 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 138893546 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 139063357 # number of overall hits
-system.cpu1.dcache.overall_hits::total 139063357 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 6025315 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 6025315 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 6706823 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 6706823 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 630176 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 630176 # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 421123 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 421123 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 264252 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 264252 # number of LoadLockedReq misses
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-system.cpu1.dcache.StoreCondReq_misses::total 195781 # number of StoreCondReq misses
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-system.cpu1.dcache.demand_misses::total 12732138 # number of demand (read+write) misses
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-system.cpu1.dcache.overall_misses::total 13362314 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 87326420147 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 87326420147 # number of ReadReq miss cycles
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-system.cpu1.dcache.WriteReq_miss_latency::total 117804291686 # number of WriteReq miss cycles
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-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13004978477 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3882326694 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 3882326694 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.StoreCondReq_miss_latency::total 4150746008 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 4758000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 4758000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 205130711833 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 205130711833 # number of demand (read+write) miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 205130711833 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 81181276 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 81181276 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 70444408 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 70444408 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.SoftPFReq_accesses::total 799987 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 479130 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total 479130 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1921681 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1921681 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu1.dcache.StoreCondReq_accesses::total 1879220 # number of StoreCondReq accesses(hits+misses)
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-system.cpu1.dcache.demand_accesses::total 151625684 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 152425671 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074221 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.074221 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.095207 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.095207 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787733 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787733 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.878933 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.878933 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.137511 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.137511 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.104182 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.104182 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_miss_rate::total 0.083971 # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.087664 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14493.253904 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14493.253904 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17564.842801 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17564.842801 # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 30881.662785 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 30881.662785 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14691.758980 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14691.758980 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21200.964384 # average StoreCondReq miss latency
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.130341 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.090860 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14925.014868 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14925.014868 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17909.397106 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17909.397106 # average WriteReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 32070.008154 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 32070.008154 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14669.910187 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14669.910187 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21204.504696 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21204.504696 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16111.254200 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 16111.254200 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15351.436273 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15351.436273 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 3328310 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 18296285 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 353421 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 675053 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.417409 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 27.103479 # average number of cycles each access was blocked
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16494.196658 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 16494.196658 # average overall miss latency
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+system.cpu1.dcache.overall_avg_miss_latency::total 15716.654954 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 3725007 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 19991584 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 377661 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 721598 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.863362 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 27.704600 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3264704 # number of writebacks
-system.cpu1.dcache.writebacks::total 3264704 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3035971 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 3035971 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5416489 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 5416489 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3258 # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3258 # number of WriteInvalidateReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 136728 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 136728 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 8452460 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 8452460 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 8452460 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 8452460 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2989344 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 2989344 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1290334 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1290334 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 630111 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 630111 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 417865 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 417865 # number of WriteInvalidateReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127524 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127524 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195781 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 195781 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4279678 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4279678 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 4909789 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 4909789 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 39357294362 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 39357294362 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 22683763866 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 22683763866 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 12612160940 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 12612160940 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12265252837 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12265252837 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1674709739 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1674709739 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3848237992 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3848237992 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 4609500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 4609500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 62041058228 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 62041058228 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 74653219168 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 74653219168 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 688989750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 688989750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 785556502 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 785556502 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1474546252 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1474546252 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036823 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036823 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018317 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018317 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787652 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787652 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.872133 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.872133 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066361 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066361 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.104182 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.104182 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028225 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028225 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032211 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.032211 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13165.863267 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13165.863267 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17579.761415 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17579.761415 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 20015.776490 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 20015.776490 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 29352.189911 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 29352.189911 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13132.506344 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13132.506344 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19655.829687 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19655.829687 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 3504875 # number of writebacks
+system.cpu1.dcache.writebacks::total 3504875 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3270021 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 3270021 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5779466 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 5779466 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::cpu1.data 3415 # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.WriteInvalidateReq_mshr_hits::total 3415 # number of WriteInvalidateReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 132178 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 132178 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 9049487 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 9049487 # number of demand (read+write) MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 9049487 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 3170822 # number of ReadReq MSHR misses
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+system.cpu1.dcache.WriteReq_mshr_misses::total 1362175 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 671771 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 671771 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 445578 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 445578 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 127605 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 127605 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195366 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 195366 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.demand_mshr_misses::total 4532997 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.overall_mshr_misses::total 5204768 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 7126 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 7126 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 7600 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 7600 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 14726 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 14726 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42364690330 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42364690330 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24508372089 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24508372089 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14203530799 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14203530799 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 13616215076 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 13616215076 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1679833771 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1679833771 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3840214031 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3840214031 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 3660000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 3660000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 66873062419 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 66873062419 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 81076593218 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 81076593218 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 831425000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 831425000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 995372500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 995372500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1826797500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1826797500 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037701 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037701 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018936 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018936 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.797134 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.797134 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.870487 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.870487 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064023 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.064023 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100258 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100258 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029050 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.029050 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033176 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.033176 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13360.791091 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13360.791091 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17992.087719 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17992.087719 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21143.411667 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21143.411667 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 30558.544354 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 30558.544354 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13164.325622 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13164.325622 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19656.511527 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19656.511527 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14496.664989 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14496.664989 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15204.975034 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15204.975034 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14752.505333 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 14752.505333 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15577.369293 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15577.369293 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116674.852652 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 116674.852652 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 130970.065789 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 130970.065789 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124052.526144 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124052.526144 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 5667991 # number of replacements
-system.cpu1.icache.tags.tagsinuse 501.848972 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 190104103 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 5668503 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 33.536915 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8518313865250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.848972 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980174 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.980174 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 5740789 # number of replacements
+system.cpu1.icache.tags.tagsinuse 501.866118 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 196754052 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 5741301 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 34.269942 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8518317120500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.866118 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.980207 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.980207 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 347 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 38 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 334 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 397835903 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 397835903 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 190104103 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 190104103 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 190104103 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 190104103 # number of demand (read+write) hits
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-system.cpu1.icache.ReadReq_miss_rate::total 0.030495 # miss rate for ReadReq accesses
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-system.cpu1.icache.demand_miss_rate::total 0.030495 # miss rate for demand accesses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total 10273.874329 # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::total 10273.874329 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10273.874329 # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10520.611180 # average overall miss latency
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-system.cpu1.icache.ReadReq_mshr_hits::total 311064 # number of ReadReq MSHR hits
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-system.cpu1.icache.overall_mshr_hits::total 311064 # number of overall MSHR hits
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 52921398555 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.demand_mshr_miss_latency::total 52921398555 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6131248 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6131248 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::total 6131248 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028909 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.028909 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028909 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.028909 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9336.011966 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9336.011966 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 9336.011966 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
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+system.cpu1.icache.ReadReq_mshr_hits::total 319831 # number of ReadReq MSHR hits
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+system.cpu1.icache.ReadReq_mshr_misses::total 5741336 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 5741336 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 5741336 # number of demand (read+write) MSHR misses
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+system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable
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+system.cpu1.icache.demand_mshr_miss_latency::total 54923658725 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6151998 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 6151998 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 6151998 # number of overall MSHR uncacheable cycles
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+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028308 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028308 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.028308 # mshr miss rate for demand accesses
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9566.355065 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9566.355065 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 9566.355065 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average ReadReq mshr uncacheable latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91820.865672 # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91820.865672 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.l2cache.prefetcher.num_hwpf_issued 6924956 # number of hwpf issued
-system.cpu1.l2cache.prefetcher.pfIdentified 7115948 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 165163 # number of redundant prefetches already in prefetch queue
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+system.cpu1.l2cache.prefetcher.pfIdentified 7535643 # number of prefetch candidates identified
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system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 889052 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 2136964 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13504.433199 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 11477625 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 2153158 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 5.330600 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 9723406338993 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 5663.402040 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 81.532496 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 97.953204 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3050.006780 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3697.963934 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 913.574746 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.345667 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004976 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005979 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.186158 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225706 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.055760 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.824245 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1347 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14805 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 22 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 237 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 720 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 360 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 20 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1369 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5255 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5224 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2823 # Occupied blocks per task id
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-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903625 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 249290678 # Number of tag accesses
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-system.cpu1.l2cache.ReadReq_hits::total 8564337 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 3264689 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 3264689 # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 166971 # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total 166971 # number of WriteInvalidateReq hits
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-system.cpu1.l2cache.UpgradeReq_hits::total 66098 # number of UpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 34177 # number of SCUpgradeReq hits
-system.cpu1.l2cache.SCUpgradeReq_hits::total 34177 # number of SCUpgradeReq hits
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-system.cpu1.l2cache.ReadExReq_hits::total 845253 # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 527309 # number of demand (read+write) hits
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-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 527309 # number of overall hits
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system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for demand accesses
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-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.104928 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.246024 # mshr miss rate for overall accesses
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system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 32355.267221 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 24665.159580 # average ReadReq mshr miss latency
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-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 53675.847871 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33685.706333 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33685.706333 # average WriteInvalidateReq mshr miss latency
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-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19753.023167 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14730.557686 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14730.557686 # average SCUpgradeReq mshr miss latency
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 257666.400000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34385.119811 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34385.119811 # average ReadExReq mshr miss latency
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-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency
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-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 22057.875175 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27659.641385 # average overall mshr miss latency
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-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19975.708850 # average UpgradeReq mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 29431.704298 # average overall mshr miss latency
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+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 108441.957459 # average ReadReq mshr uncacheable latency
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+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 116162.238897 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 12589327 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 10390309 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 6277 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 6277 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3264703 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 969369 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFResp 3 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1138126 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 416714 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 449544 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355754 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 472453 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 124 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1246255 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1097731 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11337166 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 14775069 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416528 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1186159 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 27714922 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 362785648 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 551966772 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1534872 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4319536 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 920606828 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4866324 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 20006897 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.227379 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.419140 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 13189135 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 10749038 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 7600 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3504874 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 1040151 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFResp 17 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1162830 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 444302 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 468816 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 354419 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 478843 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1323230 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1164313 # Transaction distribution
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+system.cpu1.toL2Bus.pkt_size::total 961493456 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 5242184 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 21082310 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 1.277260 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.447646 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 15457744 77.26% 77.26% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 4549153 22.74% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 15237020 72.27% 72.27% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 5845290 27.73% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 20006897 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 11420254845 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 21082310 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 12037419620 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 196151972 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 200301486 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8513145317 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 8624197196 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7729223292 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 8185098674 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 225599484 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 220844820 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 647309419 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 711986885 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40298 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40298 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136633 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29905 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40346 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40346 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136632 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29904 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
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+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47732 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122608 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231174 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231174 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353862 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47746 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 353956 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 155738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338712 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7338712 # Cumulative packet size per connected master and slave (bytes)
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system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7496536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36251000 # Layer occupancy (ticks)
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+system.iobus.reqLayer0.occupancy 36253000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 607686128 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 607574888 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 92706000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 92713000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 148478785 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 148591827 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks)
system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115568 # number of replacements
-system.iocache.tags.tagsinuse 11.294495 # Cycle average of tags in use
+system.iocache.tags.replacements 115612 # number of replacements
+system.iocache.tags.tagsinuse 11.304105 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115584 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115628 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 9116942023000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.849176 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 7.445319 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.240573 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.465332 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.705906 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 9116941730000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.838498 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 7.465607 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.239906 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.466600 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.706507 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1040640 # Number of tag accesses
-system.iocache.tags.data_accesses 1040640 # Number of data accesses
+system.iocache.tags.tag_accesses 1041036 # Number of tag accesses
+system.iocache.tags.data_accesses 1041036 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8859 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8896 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses
system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8859 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8899 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8903 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8943 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8859 # number of overall misses
-system.iocache.overall_misses::total 8899 # number of overall misses
+system.iocache.overall_misses::realview.ide 8903 # number of overall misses
+system.iocache.overall_misses::total 8943 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::realview.ide 1636729691 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 1641925191 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 1642618319 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 1647813819 # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19864825652 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 19864825652 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19871992742 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 19871992742 # number of WriteInvalidateReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::realview.ide 1636729691 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 1642294191 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::realview.ide 1642618319 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 1648182819 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles
-system.iocache.overall_miss_latency::realview.ide 1636729691 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 1642294191 # number of overall miss cycles
+system.iocache.overall_miss_latency::realview.ide 1642618319 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 1648182819 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8859 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8896 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8859 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8899 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8903 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8943 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8859 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8899 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8903 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8943 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::realview.ide 184753.323287 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 184568.928844 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 184501.664495 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 184319.219128 # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186125.718200 # average WriteInvalidateReq miss latency
-system.iocache.WriteInvalidateReq_avg_miss_latency::total 186125.718200 # average WriteInvalidateReq miss latency
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+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 39633.758490 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32967.837039 # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 38046.017555 # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17843.229524 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17820.065753 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17831.836625 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17802.173178 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17806.479891 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17804.365073 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 80406.356563 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 80557.040745 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 80468.156601 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 80568.408311 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 81192.738269 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74769.755661 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 84855.079113 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 135981.037396 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80381.745054 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 80581.332814 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75142.970070 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84862.417955 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 135884.728059 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 109478.788986 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 149269.737495 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 89069.623807 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 110640.240175 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143934.075467 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 104913.026316 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 136286.638103 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60374.894336 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 146626.827598 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64014.925373 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97247.419180 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 120682.970888 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 855568 # Transaction distribution
-system.membus.trans_dist::ReadResp 855568 # Transaction distribution
-system.membus.trans_dist::WriteReq 38542 # Transaction distribution
-system.membus.trans_dist::WriteResp 38542 # Transaction distribution
-system.membus.trans_dist::Writeback 1173701 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 661649 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 661649 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 438223 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 309934 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 117397 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
-system.membus.trans_dist::ReadExReq 139893 # Transaction distribution
-system.membus.trans_dist::ReadExResp 122444 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122608 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 1049844 # Transaction distribution
+system.membus.trans_dist::ReadResp 1049844 # Transaction distribution
+system.membus.trans_dist::WriteReq 38779 # Transaction distribution
+system.membus.trans_dist::WriteResp 38779 # Transaction distribution
+system.membus.trans_dist::Writeback 1370148 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 687460 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 687460 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 443336 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 306800 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 120479 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
+system.membus.trans_dist::ReadExReq 155568 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137698 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122614 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 78 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 26394 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4925384 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 5074464 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335910 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 335910 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 5410374 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155738 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27506 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5597252 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 5747450 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335773 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 335773 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6083223 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155744 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 572 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 52788 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 162304200 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 162513298 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14098112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14098112 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 176611410 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 651055 # Total snoops (count)
-system.membus.snoop_fanout::samples 3600660 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55012 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 189917440 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 190128768 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14086528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 14086528 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 204215296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 650589 # Total snoops (count)
+system.membus.snoop_fanout::samples 4133180 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3600660 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4133180 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3600660 # Request fanout histogram
-system.membus.reqLayer0.occupancy 98274497 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 4133180 # Request fanout histogram
+system.membus.reqLayer0.occupancy 98178497 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 22081484 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 22861986 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 10699049257 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 12090027529 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 5725496770 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 6852398799 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151866715 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 152088673 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 4566673 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 4559437 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38542 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38542 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2358990 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 933261 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 826411 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 489333 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 321493 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 810826 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 208 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 208 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 288168 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 288168 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7677415 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6169065 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 13846480 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 255017262 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 196496484 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 451513746 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1675443 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 8934179 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012956 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.113084 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 4896771 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4889534 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38779 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38779 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2596817 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 959438 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 852557 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 496684 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 319053 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 815737 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 143 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 143 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 305200 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 305200 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8223954 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6618870 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 14842824 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 276507544 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 214143912 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 490651456 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1673717 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9649223 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012003 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.108901 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 8818430 98.70% 98.70% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115749 1.30% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9533399 98.80% 98.80% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115824 1.20% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 8934179 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 7984163233 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 9649223 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 8593373447 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2491500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2556000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4301185209 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 4622045284 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3898685571 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 4138277748 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13668 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 13964 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5222 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 5482 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
sim_ticks 51320468905000 # Number of ticks simulated
final_tick 51320468905000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 112338 # Simulator instruction rate (inst/s)
-host_op_rate 131995 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6738935517 # Simulator tick rate (ticks/s)
-host_mem_usage 657468 # Number of bytes of host memory used
-host_seconds 7615.52 # Real time elapsed on the host
+host_inst_rate 115752 # Simulator instruction rate (inst/s)
+host_op_rate 136007 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6943747154 # Simulator tick rate (ticks/s)
+host_mem_usage 724128 # Number of bytes of host memory used
+host_seconds 7390.89 # Real time elapsed on the host
sim_insts 855512158 # Number of instructions simulated
sim_ops 1005211605 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 7197092 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8381734 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8381734 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 33661 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 33682 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 67343 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 73626554579 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 73626554579 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 56871439750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18132.044766 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17902.025238 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17902.025238 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170713.451769 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170713.451769 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 167130.276349 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 167130.276349 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168921.305377 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168921.305377 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 15070815 # number of replacements
system.cpu.icache.tags.tagsinuse 511.953323 # Cycle average of tags in use
system.cpu.icache.demand_mshr_misses::total 15071548 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 15071548 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 15071548 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total 21295 # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 21295 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total 21295 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 179787086612 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 179787086612 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 179787086612 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11928.906481 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11928.906481 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74431.051890 # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74431.051890 # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74431.051890 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1159288 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65272.997993 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 84629 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 667358 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 758173 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 21295 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33661 # number of ReadReq MSHR uncacheable
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+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33682 # number of WriteReq MSHR uncacheable
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+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67343 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 237171251 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 225518000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6085544162 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71908.496638 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76902.521446 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76327.891286 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average ReadReq mshr uncacheable latency
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+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 119200.719667 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153989.267264 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153989.267264 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59931.028410 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155342.500334 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 132420.195063 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 23293786 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 23285542 # Transaction distribution
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6472392 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2085922949 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 583028 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 34186904 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.003382 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.058057 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 34275542 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.049559 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.217032 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 34071281 99.66% 99.66% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115623 0.34% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 32576878 95.04% 95.04% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1698664 4.96% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 34186904 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 34275542 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 25901169608 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 909000 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 14066304 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 157288413 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3023 # Total snoops (count)
-system.membus.snoop_fanout::samples 2488136 # Request fanout histogram
+system.membus.snoop_fanout::samples 2576774 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2488136 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2576774 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2488136 # Request fanout histogram
+system.membus.snoop_fanout::total 2576774 # Request fanout histogram
system.membus.reqLayer0.occupancy 104078000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 33000 # Layer occupancy (ticks)
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 929959 # Simulator instruction rate (inst/s)
-host_op_rate 1092854 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48276126697 # Simulator tick rate (ticks/s)
-host_mem_usage 712572 # Number of bytes of host memory used
-host_seconds 1058.73 # Real time elapsed on the host
+host_inst_rate 1198732 # Simulator instruction rate (inst/s)
+host_op_rate 1408707 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 717580 # Number of bytes of host memory used
+host_seconds 821.34 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
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+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
+system.membus.snoop_fanout::samples 3693822 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3583537 # Request fanout histogram
+system.membus.snoop_fanout::total 3693822 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
sim_ticks 47216814145000 # Number of ticks simulated
final_tick 47216814145000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1225013 # Simulator instruction rate (inst/s)
-host_op_rate 1441119 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 59296512316 # Simulator tick rate (ticks/s)
-host_mem_usage 723320 # Number of bytes of host memory used
-host_seconds 796.28 # Real time elapsed on the host
+host_inst_rate 1152960 # Simulator instruction rate (inst/s)
+host_op_rate 1356355 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 55808802200 # Simulator tick rate (ticks/s)
+host_mem_usage 723640 # Number of bytes of host memory used
+host_seconds 846.05 # Real time elapsed on the host
sim_insts 975457230 # Number of instructions simulated
sim_ops 1147538415 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 154048 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.itb.walker 128704 # Number of bytes read from this memory
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-system.physmem.bytes_read::cpu0.data 35234584 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 222912 # Number of bytes read from this memory
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-system.physmem.bytes_read::total 81399700 # Number of bytes read from this memory
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-system.physmem.bytes_inst_read::total 6549372 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 100563072 # Number of bytes written to this memory
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system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory
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-system.physmem.num_reads::cpu0.dtb.walker 2407 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.itb.walker 2011 # Number of read requests responded to by this memory
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system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu0.itb.walker 2726 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu0.data 746230 # Total read bandwidth from this memory (bytes/s)
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-system.physmem.bw_read::cpu1.inst 55873 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 814879 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8745 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1723956 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 82835 # Instruction read bandwidth from this memory (bytes/s)
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-system.physmem.bw_inst_read::total 138708 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2129815 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 441 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 82665 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::cpu1.inst 55899 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_read::total 1722864 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 2726 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 82835 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 746670 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 4721 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 4684 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 55873 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 814879 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8745 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 3854211 # Total bandwidth to/from this memory (bytes/s)
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system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.cpu0.op_class::total 585300003 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 13253 # number of quiesce instructions executed
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-system.cpu0.dcache.SoftPFReq_hits::total 215655 # number of SoftPFReq hits
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system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036966 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
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system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.760429 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.760429 # miss rate for WriteInvalidateReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054554 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054554 # miss rate for LoadLockedReq accesses
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system.cpu0.dcache.overall_miss_rate::total 0.032139 # miss rate for overall accesses
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.tags.warmup_cycle 5759896500 # Cycle when the warmup percentage was hit.
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system.cpu0.icache.ReadReq_accesses::total 497752489 # number of ReadReq accesses(hits+misses)
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
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system.cpu0.l2cache.tags.warmup_cycle 290949000 # Cycle when the warmup percentage was hit.
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-system.cpu0.l2cache.ReadReq_hits::total 8326575 # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks 4469723 # number of Writeback hits
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system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 366654 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 728076 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 30193699 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706772 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694376897 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 30195318 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 354706580 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 694464585 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1466616 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 2912304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 1053462589 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 3346385 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 20385280 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.155096 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.361996 # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total 1053550085 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 3357578 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 20506010 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.181419 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.385365 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 17223609 84.49% 84.49% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 3161671 15.51% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 16785836 81.86% 81.86% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 3720174 18.14% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 20385280 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 20506010 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dcache.tags.data_accesses 348813711 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 83697564 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 83697564 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 76990336 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 76990336 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 76990302 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 76990302 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187854 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 187854 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63447 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 63447 # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 63438 # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total 63438 # number of WriteInvalidateReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 2062256 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 2062256 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048907 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 2048907 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 160687900 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 160687900 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 160875754 # number of overall hits
-system.cpu1.dcache.overall_hits::total 160875754 # number of overall hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 2048921 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 2048921 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 160687866 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 160687866 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 160875720 # number of overall hits
+system.cpu1.dcache.overall_hits::total 160875720 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 3358222 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 3358222 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1453140 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1453140 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1453174 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1453174 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 792351 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 792351 # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427052 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 427052 # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 427061 # number of WriteInvalidateReq misses
+system.cpu1.dcache.WriteInvalidateReq_misses::total 427061 # number of WriteInvalidateReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 146820 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 146820 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158842 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 158842 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4811362 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4811362 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5603713 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5603713 # number of overall misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 158828 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 158828 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4811396 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 4811396 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 5603747 # number of overall misses
+system.cpu1.dcache.overall_misses::total 5603747 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 87055786 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 87055786 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 78443476 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_miss_rate::total 0.018525 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.808352 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.808352 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870648 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870648 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.870666 # miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.870666 # miss rate for WriteInvalidateReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.066462 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.066462 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071947 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071947 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.071941 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.071941 # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029072 # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total 0.029072 # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033660 # miss rate for overall accesses
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 4030826 # number of writebacks
-system.cpu1.dcache.writebacks::total 4030826 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 4032690 # number of writebacks
+system.cpu1.dcache.writebacks::total 4032690 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 4741297 # number of replacements
system.cpu1.icache.tags.tagsinuse 496.426080 # Cycle average of tags in use
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 2278914 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 13451.937852 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 10861278 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 2294953 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 4.732680 # Average number of references to valid blocks.
-system.cpu1.l2cache.tags.warmup_cycle 9726491516500 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 5180.760257 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 68.434503 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 91.707533 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2828.453932 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 5282.581627 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.316209 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004177 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.172635 # Average percentage of cache occupancy
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-system.cpu1.l2cache.tags.occ_percent::total 0.821041 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 105 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15934 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 5 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 64 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1583 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5963 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4534 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 3771 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006409 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.972534 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 254019378 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 254019378 # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 325118 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141158 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4217165 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data 3057891 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 7741332 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 4030826 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 4030826 # number of Writeback hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161366 # number of WriteInvalidateReq hits
-system.cpu1.l2cache.WriteInvalidateReq_hits::total 161366 # number of WriteInvalidateReq hits
-system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3865 # number of UpgradeReq hits
-system.cpu1.l2cache.UpgradeReq_hits::total 3865 # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 614191 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 614191 # number of ReadExReq hits
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+system.cpu1.l2cache.tags.sampled_refs 2292767 # Sample count of references to valid blocks.
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+system.cpu1.l2cache.tags.warmup_cycle 9713557209000 # Cycle when the warmup percentage was hit.
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+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 4452 # Occupied blocks per task id
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+system.cpu1.l2cache.tags.tag_accesses 254014080 # Number of tag accesses
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+system.cpu1.l2cache.ReadReq_hits::total 7740959 # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks 4032690 # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total 4032690 # number of Writeback hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 161150 # number of WriteInvalidateReq hits
+system.cpu1.l2cache.WriteInvalidateReq_hits::total 161150 # number of WriteInvalidateReq hits
+system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 3831 # number of UpgradeReq hits
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system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
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system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 9645413 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 9645413 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 6383 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 6383 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 4030826 # Transaction distribution
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system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 426846 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 426846 # Transaction distribution
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-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 158842 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 296298 # Transaction distribution
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+system.cpu1.toL2Bus.trans_dist::UpgradeResp 296327 # Transaction distribution
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system.cpu1.toL2Bus.trans_dist::ReadExResp 1315890 # Transaction distribution
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system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 364008 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 835436 # Packet count per connected master and slave (bytes)
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system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 303476296 # Cumulative packet size per connected master and slave (bytes)
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system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1456032 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 3341744 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 952853588 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 3730448 # Total snoops (count)
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-system.cpu1.toL2Bus.snoop_fanout::mean 3.184989 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.388288 # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total 952972884 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 3837128 # Total snoops (count)
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+system.cpu1.toL2Bus.snoop_fanout::mean 1.220254 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.414418 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 15708784 81.50% 81.50% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 3565530 18.50% 100.00% # Request fanout histogram
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+system.cpu1.toL2Bus.snoop_fanout::2 4272016 22.03% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 19274314 # Request fanout histogram
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+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
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system.iobus.trans_dist::ReadReq 40295 # Transaction distribution
system.iobus.trans_dist::ReadResp 40295 # Transaction distribution
system.iobus.trans_dist::WriteReq 136634 # Transaction distribution
system.iocache.writebacks::writebacks 106694 # number of writebacks
system.iocache.writebacks::total 106694 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1759966 # number of replacements
-system.l2c.tags.tagsinuse 62842.185631 # Cycle average of tags in use
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-system.l2c.tags.occ_blocks::cpu0.inst 3338.956610 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 6965.181537 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 309.496433 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 430.211698 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 2959.236338 # Average occupied blocks per requestor
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+system.l2c.tags.avg_refs 2.037702 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 483416500 # Cycle when the warmup percentage was hit.
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+system.l2c.tags.occ_blocks::cpu0.itb.walker 57.110376 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 3318.609191 # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu1.inst 2976.403767 # Average occupied blocks per requestor
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+system.l2c.tags.occ_task_id_blocks::1023 227 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 58530 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 229 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
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+system.l2c.Writeback_accesses::total 2756140 # number of Writeback accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu0.data 600394 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::cpu1.data 259059 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.WriteInvalidateReq_accesses::total 859453 # number of WriteInvalidateReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 71869 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 64871 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 136740 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data 9285 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 8740 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 18025 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 579860 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 589179 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 1169039 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 8619 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 6546 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 567933 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 1507985 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 8835 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 7041 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 523623 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 1470023 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 4100605 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 8619 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 6546 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 567933 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 1507985 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 8835 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 7041 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 523623 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 1470023 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 4100605 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.307211 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.102641 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.197817 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.491692 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.078770 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.215304 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.165137 # miss rate for ReadReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.798347 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.620067 # miss rate for WriteInvalidateReq accesses
+system.l2c.WriteInvalidateReq_miss_rate::total 0.744610 # miss rate for WriteInvalidateReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.813271 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.833855 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.823036 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.838772 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.853776 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.846047 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.651261 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.709974 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.680852 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.307211 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.102641 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.372178 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.491692 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.078770 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.413566 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.312161 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.276134 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.307211 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.102641 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.372178 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.392643 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.491692 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.078770 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.413566 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.312161 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 1464604 # number of writebacks
-system.l2c.writebacks::total 1464604 # number of writebacks
+system.l2c.writebacks::writebacks 1464224 # number of writebacks
+system.l2c.writebacks::total 1464224 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 575939 # Transaction distribution
-system.membus.trans_dist::ReadResp 575939 # Transaction distribution
-system.membus.trans_dist::WriteReq 38831 # Transaction distribution
-system.membus.trans_dist::WriteResp 38831 # Transaction distribution
-system.membus.trans_dist::Writeback 1571298 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 742240 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 742240 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 327418 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 314341 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 148936 # Transaction distribution
-system.membus.trans_dist::ReadExReq 965776 # Transaction distribution
-system.membus.trans_dist::ReadExResp 778482 # Transaction distribution
+system.membus.trans_dist::ReadReq 575153 # Transaction distribution
+system.membus.trans_dist::ReadResp 575153 # Transaction distribution
+system.membus.trans_dist::WriteReq 38802 # Transaction distribution
+system.membus.trans_dist::WriteResp 38802 # Transaction distribution
+system.membus.trans_dist::Writeback 1570918 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 742110 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 742110 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 328170 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 314483 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 149857 # Transaction distribution
+system.membus.trans_dist::ReadExReq 965890 # Transaction distribution
+system.membus.trans_dist::ReadExResp 778455 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122570 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27558 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6332069 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 6482289 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 6331701 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 6481921 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 337982 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 337982 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 6820271 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 6819903 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155677 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 55116 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215456868 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 215667865 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 215372636 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 215583633 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14229440 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 14229440 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 229897305 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 229813073 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 4414869 # Request fanout histogram
+system.membus.snoop_fanout::samples 4535526 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4414869 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4535526 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4414869 # Request fanout histogram
+system.membus.snoop_fanout::total 4535526 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 3713925 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3713925 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38831 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38831 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2756939 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 859574 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 859574 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 330257 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 317211 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 647468 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1357089 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1357089 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8689428 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7301285 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 15990713 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301218837 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249930820 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 551149657 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 117306 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 9368496 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.012344 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.110415 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 3711525 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 3711525 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38802 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38802 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2756140 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 859453 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 859453 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 330303 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 317258 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 647561 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1356474 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1356474 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 8686436 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7297334 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 15983770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 301115229 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 249782916 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 550898145 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 117325 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9485599 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.012192 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.109740 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 9252852 98.77% 98.77% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115644 1.23% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9369955 98.78% 98.78% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115644 1.22% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 9368496 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 9485599 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1276359 # Simulator instruction rate (inst/s)
-host_op_rate 1499931 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 66258489115 # Simulator tick rate (ticks/s)
-host_mem_usage 712024 # Number of bytes of host memory used
-host_seconds 771.39 # Real time elapsed on the host
+host_inst_rate 1196191 # Simulator instruction rate (inst/s)
+host_op_rate 1405721 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62096813616 # Simulator tick rate (ticks/s)
+host_mem_usage 713636 # Number of bytes of host memory used
+host_seconds 823.09 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 6175776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2238699610 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 116338 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 36147883 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.003196 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.056441 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 36258168 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.034933 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.183610 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 36032362 99.68% 99.68% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 34991563 96.51% 96.51% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1266605 3.49% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 36147883 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 36258168 # Request fanout histogram
system.iobus.trans_dist::ReadReq 40246 # Transaction distribution
system.iobus.trans_dist::ReadResp 40246 # Transaction distribution
system.iobus.trans_dist::WriteReq 136515 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 227117498 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3583537 # Request fanout histogram
+system.membus.snoop_fanout::samples 3693822 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3583537 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3693822 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3583537 # Request fanout histogram
+system.membus.snoop_fanout::total 3693822 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
---------- Begin Simulation Statistics ----------
-sim_seconds 47.367818 # Number of seconds simulated
-sim_ticks 47367817574000 # Number of ticks simulated
-final_tick 47367817574000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.526955 # Number of seconds simulated
+sim_ticks 47526954967000 # Number of ticks simulated
+final_tick 47526954967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 678056 # Simulator instruction rate (inst/s)
-host_op_rate 798173 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38043399524 # Simulator tick rate (ticks/s)
-host_mem_usage 751768 # Number of bytes of host memory used
-host_seconds 1245.10 # Real time elapsed on the host
-sim_insts 844246943 # Number of instructions simulated
-sim_ops 993804803 # Number of ops (including micro ops) simulated
+host_inst_rate 679404 # Simulator instruction rate (inst/s)
+host_op_rate 799114 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36258651928 # Simulator tick rate (ticks/s)
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+host_seconds 1310.78 # Real time elapsed on the host
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory
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system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s)
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 352 # Number of times write queue was full causing retry
-system.physmem.totGap 47367814519500 # Total gap between requests
+system.physmem.numWrRetry 406 # Number of times write queue was full causing retry
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
-system.physmem.readPktSize::3 37 # Read request sizes (log2)
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system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.bytesPerActivate::mean 175.690629 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 106.318755 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 249.924527 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 526198 64.72% 64.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 156067 19.20% 83.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 35208 4.33% 88.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 17256 2.12% 90.37% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::640-767 8107 1.00% 92.85% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::896-1023 5625 0.69% 94.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 46276 5.69% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 813055 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 73772 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 9.277314 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 118.735455 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 73768 99.99% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::1024-2047 2 0.00% 100.00% # Reads before turning the bus around for writes
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+system.physmem.bytesPerActivate::1024-1151 52683 4.99% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 1054851 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 20.977674 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::stdev 19.656514 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::160-175 12 0.02% 99.70% # Writes before turning the bus around for reads
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-system.physmem.totQLat 20326500723 # Total ticks spent queuing
-system.physmem.totMemAccLat 33159206973 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 3422055000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 29699.26 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::total 92018 # Writes before turning the bus around for reads
+system.physmem.totQLat 36585898476 # Total ticks spent queuing
+system.physmem.totMemAccLat 55223735976 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 4970090000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 36806.07 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48449.26 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.92 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 2.09 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.87 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 2.15 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 55556.07 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 2.50 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 2.56 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 0.02 # Data bus utilization in percentage
+system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.16 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing
-system.physmem.readRowHits 509481 # Number of row buffer hits during reads
-system.physmem.writeRowHits 909439 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 74.44 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
-system.physmem.avgGap 20763390.98 # Average gap between requests
-system.physmem.pageHitRate 63.57 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 3169991160 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 1729657875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2640253200 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 5060782800 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1178038765890 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 27387322041000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 31671796931685 # Total energy per rank (pJ)
-system.physmem_0.averagePower 668.635370 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 45560807372172 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1581715460000 # Time in different power states
+system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing
+system.physmem.readRowHits 744165 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1049121 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 74.86 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 56.58 # Row buffer hit rate for writes
+system.physmem.avgGap 16404601.42 # Average gap between requests
+system.physmem.pageHitRate 62.96 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 4105851120 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 2240295750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 3892535400 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 6128142480 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1214897373855 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 27450471155250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 31785964742895 # Total energy per rank (pJ)
+system.physmem_0.averagePower 668.798736 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 45665609957576 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1587029340000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 225294290828 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 274315218424 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 2976704640 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 1624194000 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2698113600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 4967438400 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3093835439760 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1169320459140 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 27394969678500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 31670392028040 # Total energy per rank (pJ)
-system.physmem_1.averagePower 668.605711 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 45573545582628 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1581715460000 # Time in different power states
+system.physmem_1.actEnergy 3868822440 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 2110964625 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 3860766000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 5886555120 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1202076105075 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 27461717882250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 31783750484550 # Total energy per rank (pJ)
+system.physmem_1.averagePower 668.752146 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 45684364167822 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1587029340000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 212554603622 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 255557515928 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 95467 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 95467 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8616 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 72889 # Level at which table walker walks with long descriptors terminate
-system.cpu0.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
-system.cpu0.dtb.walker.walkWaitTime::samples 95458 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::mean 0.225230 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::stdev 69.587670 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0-2047 95457 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::20480-22527 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 95458 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 81514 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 17324.683490 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 15769.335506 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 10694.107977 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-65535 81100 99.49% 99.49% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::65536-131071 359 0.44% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::131072-196607 15 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::196608-262143 17 0.02% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::262144-327679 14 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::327680-393215 5 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 101631 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 101631 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9048 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76119 # Level at which table walker walks with long descriptors terminate
+system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting
+system.cpu0.dtb.walker.walkWaitTime::samples 101620 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::mean 0.113167 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::stdev 36.075158 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0-1023 101619 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 101620 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 85178 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-65535 84047 98.67% 98.67% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::65536-131071 953 1.12% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::131072-196607 46 0.05% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::196608-262143 63 0.07% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::262144-327679 53 0.06% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 81514 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walksPending::samples 1873275212 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.115454 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -216276296 -11.55% -11.55% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 2089551508 111.55% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 1873275212 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 72890 89.43% 89.43% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 8616 10.57% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 81506 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 95467 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 85178 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walksPending::samples 6479942056 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.123756 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -801929896 -12.38% -12.38% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 7281871952 112.38% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 6479942056 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 76120 89.38% 89.38% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 9048 10.62% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 85168 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101631 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 95467 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 81506 # Table walker requests started/completed, data/inst
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+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85168 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 81506 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 176973 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85168 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 186799 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 81219280 # DTB read hits
-system.cpu0.dtb.read_misses 71070 # DTB read misses
-system.cpu0.dtb.write_hits 73504932 # DTB write hits
-system.cpu0.dtb.write_misses 24397 # DTB write misses
+system.cpu0.dtb.read_hits 83767358 # DTB read hits
+system.cpu0.dtb.read_misses 74871 # DTB read misses
+system.cpu0.dtb.write_hits 75914688 # DTB write hits
+system.cpu0.dtb.write_misses 26760 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 38298 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 32159 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 4007 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 3900 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 10240 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 81290350 # DTB read accesses
-system.cpu0.dtb.write_accesses 73529329 # DTB write accesses
+system.cpu0.dtb.perms_faults 8424 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 83842229 # DTB read accesses
+system.cpu0.dtb.write_accesses 75941448 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 154724212 # DTB hits
-system.cpu0.dtb.misses 95467 # DTB misses
-system.cpu0.dtb.accesses 154819679 # DTB accesses
+system.cpu0.dtb.hits 159682046 # DTB hits
+system.cpu0.dtb.misses 101631 # DTB misses
+system.cpu0.dtb.accesses 159783677 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 56383 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 56383 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walksLongTerminationLevel::Level2 751 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walksLongTerminationLevel::Level3 50468 # Level at which table walker walks with long descriptors terminate
-system.cpu0.itb.walker.walkWaitTime::samples 56383 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 56383 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 56383 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkCompletionTime::samples 51219 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 19351.129327 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 17618.924664 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 12629.312385 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-32767 47792 93.31% 93.31% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::32768-65535 2988 5.83% 99.14% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::65536-98303 157 0.31% 99.45% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::98304-131071 221 0.43% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::131072-163839 13 0.03% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::163840-196607 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::196608-229375 16 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::294912-327679 7 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::327680-360447 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::total 51219 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walks 55722 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 55722 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walksLongTerminationLevel::Level2 543 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49598 # Level at which table walker walks with long descriptors terminate
+system.cpu0.itb.walker.walkWaitTime::samples 55722 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 55722 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 55722 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkCompletionTime::samples 50141 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-65535 48785 97.30% 97.30% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::65536-131071 1144 2.28% 99.58% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::131072-196607 57 0.11% 99.69% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::196608-262143 79 0.16% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::262144-327679 56 0.11% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::total 50141 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 50468 98.53% 98.53% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 751 1.47% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 51219 # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::4K 49598 98.92% 98.92% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 543 1.08% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 50141 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 56383 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 56383 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55722 # Table walker requests started/completed, data/inst
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system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 51219 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 51219 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 107602 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 434853798 # ITB inst hits
-system.cpu0.itb.inst_misses 56383 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50141 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50141 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 105863 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 444122432 # ITB inst hits
+system.cpu0.itb.inst_misses 55722 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 26912 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 22526 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 434910181 # ITB inst accesses
-system.cpu0.itb.hits 434853798 # DTB hits
-system.cpu0.itb.misses 56383 # DTB misses
-system.cpu0.itb.accesses 434910181 # DTB accesses
-system.cpu0.numCycles 94735635148 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 444178154 # ITB inst accesses
+system.cpu0.itb.hits 444122432 # DTB hits
+system.cpu0.itb.misses 55722 # DTB misses
+system.cpu0.itb.accesses 444178154 # DTB accesses
+system.cpu0.numCycles 95053909934 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 434594659 # Number of instructions committed
-system.cpu0.committedOps 509819268 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 468245604 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 368958 # Number of float alu accesses
-system.cpu0.num_func_calls 25685063 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 65742912 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 468245604 # number of integer instructions
-system.cpu0.num_fp_insts 368958 # number of float instructions
-system.cpu0.num_int_register_reads 681605000 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 371986080 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 629019 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 237888 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 113785122 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 113402508 # number of times the CC registers were written
-system.cpu0.num_mem_refs 154715442 # number of memory refs
-system.cpu0.num_load_insts 81215665 # Number of load instructions
-system.cpu0.num_store_insts 73499777 # Number of store instructions
-system.cpu0.num_idle_cycles 93677942540.842026 # Number of idle cycles
-system.cpu0.num_busy_cycles 1057692607.157978 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011165 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988835 # Percentage of idle cycles
-system.cpu0.Branches 96525602 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 354149041 69.42% 69.42% # Class of executed instruction
-system.cpu0.op_class::IntMult 1173113 0.23% 69.65% # Class of executed instruction
-system.cpu0.op_class::IntDiv 59997 0.01% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 23937 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.67% # Class of executed instruction
-system.cpu0.op_class::MemRead 81215665 15.92% 85.59% # Class of executed instruction
-system.cpu0.op_class::MemWrite 73499777 14.41% 100.00% # Class of executed instruction
+system.cpu0.committedInsts 443872382 # Number of instructions committed
+system.cpu0.committedOps 521690846 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 479475231 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 421225 # Number of float alu accesses
+system.cpu0.num_func_calls 26535732 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 67239811 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 479475231 # number of integer instructions
+system.cpu0.num_fp_insts 421225 # number of float instructions
+system.cpu0.num_int_register_reads 693782505 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 380162379 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 701849 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 304628 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 115037577 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 114748059 # number of times the CC registers were written
+system.cpu0.num_mem_refs 159672530 # number of memory refs
+system.cpu0.num_load_insts 83761106 # Number of load instructions
+system.cpu0.num_store_insts 75911424 # Number of store instructions
+system.cpu0.num_idle_cycles 93959856753.206024 # Number of idle cycles
+system.cpu0.num_busy_cycles 1094053180.793977 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.011510 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.988490 # Percentage of idle cycles
+system.cpu0.Branches 99058393 # Number of branches fetched
+system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 361081858 69.17% 69.17% # Class of executed instruction
+system.cpu0.op_class::IntMult 1125018 0.22% 69.39% # Class of executed instruction
+system.cpu0.op_class::IntDiv 61306 0.01% 69.40% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction
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+system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 43308 0.01% 69.41% # Class of executed instruction
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+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
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+system.cpu0.op_class::MemRead 83761106 16.05% 85.46% # Class of executed instruction
+system.cpu0.op_class::MemWrite 75911424 14.54% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 510121531 # Class of executed instruction
+system.cpu0.op_class::total 521984020 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 13974 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 5284481 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 474.292500 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 149186915 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5284993 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.228404 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 4077089500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 474.292500 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.926353 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.926353 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 314708854 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 314708854 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 75740068 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 75740068 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 69444390 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 69444390 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177454 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 177454 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 143100 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 143100 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1662300 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1662300 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1634095 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1634095 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 145184458 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 145184458 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 145361912 # number of overall hits
-system.cpu0.dcache.overall_hits::total 145361912 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 2820396 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 2820396 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1320543 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1320543 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 635767 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 635767 # number of SoftPFReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 746024 # number of WriteInvalidateReq misses
-system.cpu0.dcache.WriteInvalidateReq_misses::total 746024 # number of WriteInvalidateReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 156072 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 156072 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 182947 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 182947 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4140939 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4140939 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 4776706 # number of overall misses
-system.cpu0.dcache.overall_misses::total 4776706 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 39561901741 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 39561901741 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24338572363 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 24338572363 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30943018074 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30943018074 # number of WriteInvalidateReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2147538753 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2147538753 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3961701456 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 3961701456 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1248500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1248500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 63900474104 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 63900474104 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 63900474104 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 63900474104 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 78560464 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 78560464 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 70764933 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 70764933 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 813221 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 813221 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 889124 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 889124 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1818372 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1818372 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1817042 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1817042 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 149325397 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 149325397 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 150138618 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 150138618 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.035901 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.035901 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018661 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018661 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.781789 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.781789 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.839055 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.839055 # miss rate for WriteInvalidateReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085831 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.085831 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.100684 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.100684 # miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_miss_rate::total 0.027731 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031815 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.031815 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14027.073411 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14027.073411 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18430.730664 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 18430.730664 # average WriteReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41477.242118 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41477.242118 # average WriteInvalidateReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 13759.923324 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 13759.923324 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21654.913478 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21654.913478 # average StoreCondReq miss latency
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+system.cpu0.dcache.tags.sampled_refs 5414914 # Sample count of references to valid blocks.
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+system.cpu0.dcache.tags.warmup_cycle 4071814500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.206026 # Average occupied blocks per requestor
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+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
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+system.cpu0.dcache.SoftPFReq_hits::total 187802 # number of SoftPFReq hits
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+system.cpu0.dcache.WriteInvalidateReq_hits::total 131287 # number of WriteInvalidateReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::total 1831493 # number of LoadLockedReq hits
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+system.cpu0.dcache.StoreCondReq_hits::total 1787873 # number of StoreCondReq hits
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+system.cpu0.dcache.overall_hits::total 149878390 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 2964325 # number of ReadReq misses
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13711.322719 # average overall mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.l2cache.prefetcher.pfIdentified 7625539 # number of prefetch candidates identified
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975 # average overall mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553 # average ReadReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737 # average WriteReq mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116 # average overall mshr uncacheable latency
+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 10272423 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 8656546 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 26078 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 26078 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 3634622 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 896357 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1072966 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 744713 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 432357 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 330872 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 471310 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 48 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1218200 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1108311 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9087184 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15490281 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 297199 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 469779 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 25344443 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 288202388 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 584369767 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1031640 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1541304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 875145099 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 3727007 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 17787477 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.192426 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.394206 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 11389901 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 9301467 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 18033 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3655914 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 950949 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1103178 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 737778 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 440847 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 362789 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 484218 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1248974 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1125262 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10151888 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15745151 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 304033 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 517558 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 26718630 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 322272916 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 593126965 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1100312 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1778264 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 918278457 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 4307980 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 19190741 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.234424 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.423639 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 14364709 80.76% 80.76% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 3422768 19.24% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 14691964 76.56% 76.56% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 4498777 23.44% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 17787477 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 11622970748 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 19190741 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 11979643994 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 201159488 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 187059488 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 6810939722 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 7611089646 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7629819592 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 7824710310 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 168326514 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 166780001 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 277196500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 295551751 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 92509 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 92509 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 6608 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 71644 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 9 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 92500 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::mean 0.081081 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::stdev 24.659848 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0-511 92499 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walks 115983 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 115983 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11170 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89969 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting
+system.cpu1.dtb.walker.walkWaitTime::samples 115964 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::mean 0.064675 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::stdev 22.024176 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0-511 115963 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 92500 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 78261 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 18926.409693 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 17150.140934 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 13619.258696 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-65535 77412 98.92% 98.92% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-131071 724 0.93% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.04% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-262143 50 0.06% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-327679 28 0.04% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::393216-458751 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 78261 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 2425306712 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.143168 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.350244 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 2078081352 85.68% 85.68% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 347225360 14.32% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 2425306712 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 71644 91.56% 91.56% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 6608 8.44% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 78252 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 92509 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::total 115964 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 101158 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-65535 99918 98.77% 98.77% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1061 1.05% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.03% 99.86% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-262143 72 0.07% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-327679 53 0.05% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 101158 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 3223072220 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.344065 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.475063 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 2114124352 65.59% 65.59% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 1108947868 34.41% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 3223072220 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 89969 88.96% 88.96% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 11170 11.04% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 101139 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 115983 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 92509 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 78252 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 115983 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 101139 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 78252 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 170761 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 101139 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 217122 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 78277454 # DTB read hits
-system.cpu1.dtb.read_misses 68245 # DTB read misses
-system.cpu1.dtb.write_hits 71517077 # DTB write hits
-system.cpu1.dtb.write_misses 24264 # DTB write misses
+system.cpu1.dtb.read_hits 83993689 # DTB read hits
+system.cpu1.dtb.read_misses 86321 # DTB read misses
+system.cpu1.dtb.write_hits 76478778 # DTB write hits
+system.cpu1.dtb.write_misses 29662 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 32777 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 42752 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 3876 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 8314 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 78345699 # DTB read accesses
-system.cpu1.dtb.write_accesses 71541341 # DTB write accesses
+system.cpu1.dtb.perms_faults 11385 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 84080010 # DTB read accesses
+system.cpu1.dtb.write_accesses 76508440 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 149794531 # DTB hits
-system.cpu1.dtb.misses 92509 # DTB misses
-system.cpu1.dtb.accesses 149887040 # DTB accesses
+system.cpu1.dtb.hits 160472467 # DTB hits
+system.cpu1.dtb.misses 115983 # DTB misses
+system.cpu1.dtb.accesses 160588450 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 60524 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 60524 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 415 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54985 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 60524 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 60524 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 60524 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 55400 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 21598.519856 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 19393.747052 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 17485.706336 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 51757 93.42% 93.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 2619 4.73% 98.15% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 338 0.61% 98.76% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 537 0.97% 99.73% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 24 0.04% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 13 0.02% 99.80% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 37 0.07% 99.86% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 14 0.03% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::262144-294911 28 0.05% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 16 0.03% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 4 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::393216-425983 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::425984-458751 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::491520-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 55400 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 2054805852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 2054805852 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 2054805852 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 54985 99.25% 99.25% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 415 0.75% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 55400 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 60651 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 60651 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 616 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54731 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 60651 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 60651 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 60651 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 55347 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-65535 53969 97.51% 97.51% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-131071 1178 2.13% 99.64% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-196607 42 0.08% 99.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.12% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-327679 60 0.11% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.04% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 55347 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 2053569352 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 2053569352 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 2053569352 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 54731 98.89% 98.89% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 616 1.11% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 55347 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60524 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60524 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60651 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60651 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55400 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55400 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 115924 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 409921957 # ITB inst hits
-system.cpu1.itb.inst_misses 60524 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55347 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55347 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 115998 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 446979774 # ITB inst hits
+system.cpu1.itb.inst_misses 60651 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 37751 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 996 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 23091 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 29800 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 409982481 # ITB inst accesses
-system.cpu1.itb.hits 409921957 # DTB hits
-system.cpu1.itb.misses 60524 # DTB misses
-system.cpu1.itb.accesses 409982481 # DTB accesses
-system.cpu1.numCycles 94735635148 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 447040425 # ITB inst accesses
+system.cpu1.itb.hits 446979774 # DTB hits
+system.cpu1.itb.misses 60651 # DTB misses
+system.cpu1.itb.accesses 447040425 # DTB accesses
+system.cpu1.numCycles 95053909934 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 409652284 # Number of instructions committed
-system.cpu1.committedOps 483985535 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 446181756 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 565626 # Number of float alu accesses
-system.cpu1.num_func_calls 25682090 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 61510479 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 446181756 # number of integer instructions
-system.cpu1.num_fp_insts 565626 # number of float instructions
-system.cpu1.num_int_register_reads 638057436 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 352717621 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 886208 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 535956 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 102771786 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 102542500 # number of times the CC registers were written
-system.cpu1.num_mem_refs 149782083 # number of memory refs
-system.cpu1.num_load_insts 78271508 # Number of load instructions
-system.cpu1.num_store_insts 71510575 # Number of store instructions
-system.cpu1.num_idle_cycles 93767065494.048019 # Number of idle cycles
-system.cpu1.num_busy_cycles 968569653.951980 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.010224 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.989776 # Percentage of idle cycles
-system.cpu1.Branches 91673037 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 333338821 68.84% 68.84% # Class of executed instruction
-system.cpu1.op_class::IntMult 986884 0.20% 69.04% # Class of executed instruction
-system.cpu1.op_class::IntDiv 58271 0.01% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.05% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 89216 0.02% 69.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.07% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.07% # Class of executed instruction
-system.cpu1.op_class::MemRead 78271508 16.16% 85.23% # Class of executed instruction
-system.cpu1.op_class::MemWrite 71510575 14.77% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 446673984 # Number of instructions committed
+system.cpu1.committedOps 525768473 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 482657433 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 472663 # Number of float alu accesses
+system.cpu1.num_func_calls 26533376 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 68272280 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 482657433 # number of integer instructions
+system.cpu1.num_fp_insts 472663 # number of float instructions
+system.cpu1.num_int_register_reads 706740468 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 383340050 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 750974 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 430296 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 118015071 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 117677935 # number of times the CC registers were written
+system.cpu1.num_mem_refs 160465117 # number of memory refs
+system.cpu1.num_load_insts 83993061 # Number of load instructions
+system.cpu1.num_store_insts 76472056 # Number of store instructions
+system.cpu1.num_idle_cycles 93999959015.450027 # Number of idle cycles
+system.cpu1.num_busy_cycles 1053950918.549978 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011088 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988912 # Percentage of idle cycles
+system.cpu1.Branches 99666047 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 364374913 69.26% 69.26% # Class of executed instruction
+system.cpu1.op_class::IntMult 1108574 0.21% 69.47% # Class of executed instruction
+system.cpu1.op_class::IntDiv 57501 0.01% 69.48% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 68224 0.01% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu1.op_class::MemRead 83993061 15.97% 85.46% # Class of executed instruction
+system.cpu1.op_class::MemWrite 76472056 14.54% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 484255317 # Class of executed instruction
+system.cpu1.op_class::total 526074372 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 5204 # number of quiesce instructions executed
-system.cpu1.dcache.tags.replacements 4752540 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 455.880794 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 144856637 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 4753051 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 30.476559 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8382286333500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.880794 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890392 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.890392 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 149 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 304369060 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 304369060 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 73044937 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 73044937 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 67886662 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 67886662 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 184038 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 184038 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 188938 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 188938 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1611925 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1611925 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1592857 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1592857 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 140931599 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 140931599 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 141115637 # number of overall hits
-system.cpu1.dcache.overall_hits::total 141115637 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 2767627 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 2767627 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1154762 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1154762 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 498783 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 498783 # number of SoftPFReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 496292 # number of WriteInvalidateReq misses
-system.cpu1.dcache.WriteInvalidateReq_misses::total 496292 # number of WriteInvalidateReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 158321 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 158321 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 176268 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 176268 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 3922389 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 3922389 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 4421172 # number of overall misses
-system.cpu1.dcache.overall_misses::total 4421172 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 37645623046 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 37645623046 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 19534966036 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 19534966036 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 11881656902 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 11881656902 # number of WriteInvalidateReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2306877268 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2306877268 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 3770896575 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 3770896575 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1887000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1887000 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.demand_miss_latency::total 57180589082 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 57180589082 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 57180589082 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 75812564 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.WriteReq_accesses::cpu1.data 69041424 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 69041424 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 682821 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 682821 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685230 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total 685230 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1770246 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1770246 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1769125 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1769125 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 144853988 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 144853988 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 145536809 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036506 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.036506 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.016726 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.016726 # miss rate for WriteReq accesses
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.730474 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.724271 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.724271 # miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.089434 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.089434 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.099636 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.099636 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_miss_rate::total 0.027078 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.030378 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.030378 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13602.130289 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 13602.130289 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16916.876409 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 16916.876409 # average WriteReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 23940.859216 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 23940.859216 # average WriteInvalidateReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14570.886162 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14570.886162 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21392.973058 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21392.973058 # average StoreCondReq miss latency
+system.cpu1.kern.inst.quiesce 14059 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 5413042 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 455.092206 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 154856630 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5413554 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.605354 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8382280704500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.092206 # Average occupied blocks per requestor
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+system.cpu1.dcache.tags.occ_percent::total 0.888852 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 326337345 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 326337345 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 78172197 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 78172197 # number of ReadReq hits
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.037272 # miss rate for ReadReq accesses
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092962 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.028385 # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.032596 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999 # average WriteReq miss latency
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+system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316 # average WriteInvalidateReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293 # average LoadLockedReq miss latency
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 14578.000571 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 14578.000571 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 12933.355473 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 12933.355473 # average overall miss latency
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+system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3063492 # number of writebacks
-system.cpu1.dcache.writebacks::total 3063492 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 11545 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 11545 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 352 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 352 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 46682 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46682 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 11897 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 11897 # number of demand (read+write) MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 11897 # number of overall MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses::total 2756082 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 496292 # number of WriteInvalidateReq MSHR misses
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-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 176268 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 176268 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 3910492 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 4409275 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 32859790378 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 32859790378 # number of ReadReq MSHR miss cycles
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-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 9770846491 # number of SoftPFReq MSHR miss cycles
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1396307998 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1396307998 # number of LoadLockedReq MSHR miss cycles
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-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3498646925 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1819500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1819500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 50602962592 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 50602962592 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 1936116751 # number of ReadReq MSHR uncacheable cycles
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-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4100133250 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036354 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036354 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.016721 # mshr miss rate for WriteReq accesses
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-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.730474 # mshr miss rate for SoftPFReq accesses
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-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.724271 # mshr miss rate for WriteInvalidateReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.063064 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.063064 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.099636 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.099636 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026996 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.026996 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.030297 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.030297 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11922.646125 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11922.646125 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15369.905158 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15369.905158 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19589.373517 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19589.373517 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 22434.532690 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 22434.532690 # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12507.349564 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12507.349564 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19848.451931 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19848.451931 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 3550271 # number of writebacks
+system.cpu1.dcache.writebacks::total 3550271 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18006 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 18006 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 425 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 425 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44886 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44886 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 18431 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 18431 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 18431 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 18431 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 3008404 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1374025 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 1374025 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 681215 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 681215 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 497314 # number of WriteInvalidateReq MSHR misses
+system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497314 # number of WriteInvalidateReq MSHR misses
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+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 132514 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202765 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 202765 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21725 # number of ReadReq MSHR uncacheable
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+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable
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+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 41838 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38446720676 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38446720676 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21137642197 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21137642197 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605784836 # number of SoftPFReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690394742 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1807000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1807000 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu1.dcache.demand_mshr_miss_latency::total 59584362873 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73190147709 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 73190147709 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3727466501 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3727466501 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3465674500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7193141001 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037050 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037050 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018607 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018607 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787465 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787465 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.716226 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.716226 # mshr miss rate for WriteInvalidateReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069441 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069441 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106334 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106334 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028266 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032478 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.032478 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917 # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325 # average LoadLockedReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12940.305873 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12940.305873 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13692.457169 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13692.457169 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870 # average overall mshr miss latency
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+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785 # average ReadReq mshr uncacheable latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 5523110 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.341944 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 404398330 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 5523622 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 73.212528 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 8382258847250 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.341944 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969418 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.969418 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 4892397 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.394395 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 442086860 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 4892909 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 90.352561 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 8382252985250 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.394395 # Average occupied blocks per requestor
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+system.cpu1.icache.tags.occ_percent::total 0.969520 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::0 74 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 825367541 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 825367541 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 404398330 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 404398330 # number of ReadReq hits
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-system.cpu1.icache.overall_hits::total 404398330 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 5523627 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::total 5523627 # number of demand (read+write) misses
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-system.cpu1.icache.overall_misses::total 5523627 # number of overall misses
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-system.cpu1.icache.ReadReq_miss_latency::total 54612807078 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 54612807078 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 54612807078 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 409921957 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 409921957 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 409921957 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 409921957 # number of overall (read+write) accesses
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-system.cpu1.icache.ReadReq_miss_rate::total 0.013475 # miss rate for ReadReq accesses
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-system.cpu1.icache.demand_miss_rate::total 0.013475 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.013475 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9887.127983 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 9887.127983 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 9887.127983 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9887.127983 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 9887.127983 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 898852462 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 898852462 # Number of data accesses
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+system.cpu1.icache.ReadReq_hits::total 442086860 # number of ReadReq hits
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+system.cpu1.icache.overall_hits::total 442086860 # number of overall hits
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+system.cpu1.icache.demand_misses::total 4892914 # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::total 4892914 # number of overall misses
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+system.cpu1.icache.ReadReq_miss_latency::total 51771462698 # number of ReadReq miss cycles
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+system.cpu1.icache.demand_miss_latency::total 51771462698 # number of demand (read+write) miss cycles
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+system.cpu1.icache.overall_miss_latency::total 51771462698 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 446979774 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total 446979774 # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst 446979774 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total 446979774 # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst 446979774 # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total 446979774 # number of overall (read+write) accesses
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+system.cpu1.icache.ReadReq_miss_rate::total 0.010947 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010947 # miss rate for demand accesses
+system.cpu1.icache.demand_miss_rate::total 0.010947 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010947 # miss rate for overall accesses
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-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.140548 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.044326 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.049257 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.079846 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.225394 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.186673 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.186673 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167201 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.191832 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 24122.647893 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 23948.829754 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33772.870485 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 32243.321967 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 32243.321967 # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 19748.308136 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19748.308136 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14712.282892 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14712.282892 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296199.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296199.600000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 31396.349903 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 31396.349903 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25010.215568 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 24955.230230 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 29581.568346 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23525.177713 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 25643.085014 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33772.870485 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27352.810917 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.235840 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957 # average WriteInvalidateReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 301400 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 301400 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 11346555 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9442060 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 12895 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 12895 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3063492 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 747367 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1164315 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 494732 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 387368 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 328581 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 412328 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1123330 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 992188 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 11047474 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 13661084 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 335346 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 476365 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 25520269 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 353512568 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 512414548 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1234496 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1647784 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 868809396 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 4168573 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 18149089 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.215812 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.411385 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 11407818 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9339972 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 20113 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 3550271 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 1013669 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1157980 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495764 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 395206 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 367201 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 457834 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1341582 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1187599 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9786048 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15579584 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 330806 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 594855 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 26291293 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 313146936 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 585201818 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1196936 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2069904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 901615594 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 4634762 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 19271924 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 1.253755 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.435159 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 14232289 78.42% 78.42% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 3916800 21.58% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 14381570 74.62% 74.62% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 4890354 25.38% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 18149089 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 10693279996 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 19271924 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 11505600998 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 176128990 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 168563993 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 8292291078 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 7347478432 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 7012668647 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 8042476622 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 181227501 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 181503274 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 270567252 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 336447522 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40336 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40336 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136623 # Transaction distribution
-system.iobus.trans_dist::WriteResp 29895 # Transaction distribution
+system.iobus.trans_dist::ReadReq 40366 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40366 # Transaction distribution
+system.iobus.trans_dist::WriteReq 136641 # Transaction distribution
+system.iobus.trans_dist::WriteResp 29913 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 122628 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 122716 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353918 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes)
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system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
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-system.l2c.overall_avg_mshr_miss_latency::total 88062.246128 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
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+system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.529400 # mshr miss rate for WriteInvalidateReq accesses
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 622157 # Transaction distribution
-system.membus.trans_dist::ReadResp 622157 # Transaction distribution
-system.membus.trans_dist::WriteReq 38973 # Transaction distribution
-system.membus.trans_dist::WriteResp 38973 # Transaction distribution
-system.membus.trans_dist::Writeback 957695 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 636331 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 636331 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 382471 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 288753 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 111723 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 28 # Transaction distribution
-system.membus.trans_dist::ReadExReq 123220 # Transaction distribution
-system.membus.trans_dist::ReadExResp 104410 # Transaction distribution
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+system.membus.trans_dist::WriteReq 38146 # Transaction distribution
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+system.membus.trans_dist::Writeback 1227861 # Transaction distribution
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+system.membus.trans_dist::SCUpgradeReq 320224 # Transaction distribution
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system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 28184 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 4073596 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4224500 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335903 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 335903 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4560403 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155735 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5055890 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_count::total 5539258 # Packet count per connected master and slave (bytes)
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system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 56368 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 129167796 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 129380103 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14096512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 14096512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 143476615 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 581158 # Total snoops (count)
-system.membus.snoop_fanout::samples 2928688 # Request fanout histogram
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+system.membus.pkt_size_system.iocache.mem_side::total 14076224 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 182887483 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 594337 # Total snoops (count)
+system.membus.snoop_fanout::samples 3681134 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2928688 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3681134 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2928688 # Request fanout histogram
-system.membus.reqLayer0.occupancy 100579500 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 3681134 # Request fanout histogram
+system.membus.reqLayer0.occupancy 100790999 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 24544499 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 21573500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 9168550783 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 11112792344 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 4323654540 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 5991933811 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 151928439 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 151912879 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 3783137 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 3775909 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38973 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38973 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 2047649 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 890925 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 784014 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 429633 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 300246 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 729879 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 72 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 72 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 258637 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 258637 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 6917142 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4903000 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 11820142 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 229102843 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 151634764 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 380737607 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1518303 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 7628101 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.015184 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.122286 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 4327568 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 4320333 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38146 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 2374848 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 920665 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 813714 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 419012 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 331945 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 750957 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 292509 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 292509 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7096014 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6270717 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 13366731 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 236480377 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202778754 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 439259131 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1555479 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 8704899 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.013311 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.114603 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 7512273 98.48% 98.48% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115828 1.52% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 8589027 98.67% 98.67% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115872 1.33% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 7628101 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 6924291534 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 8704899 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 7795939791 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 2530500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 2526000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 3796276244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 3978610795 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3095093071 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 3846379763 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 51824462100500 # Number of ticks simulated
final_tick 51824462100500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 723017 # Simulator instruction rate (inst/s)
-host_op_rate 849578 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 41937024652 # Simulator tick rate (ticks/s)
-host_mem_usage 712044 # Number of bytes of host memory used
-host_seconds 1235.77 # Real time elapsed on the host
+host_inst_rate 684695 # Simulator instruction rate (inst/s)
+host_op_rate 804548 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 39714246392 # Simulator tick rate (ticks/s)
+host_mem_usage 713112 # Number of bytes of host memory used
+host_seconds 1304.93 # Real time elapsed on the host
sim_insts 893481288 # Number of instructions simulated
sim_ops 1049881338 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 7497734 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 8793254 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 8793254 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 33706 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 67416 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75489557525 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 75489557525 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 62224351540 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 18367.403947 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 17953.193816 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 17953.193816 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 170628.204177 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170628.204177 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 166674.110056 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166674.110056 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 168651.039813 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 168651.039813 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 13753173 # number of replacements
system.cpu.icache.tags.tagsinuse 511.880059 # Cycle average of tags in use
system.cpu.icache.demand_mshr_misses::total 13753690 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 13753690 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 13753690 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 163860958817 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 163860958817 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 163860958817 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11913.963367 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11913.963367 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 74459.988406 # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 74459.988406 # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 74459.988406 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 1292250 # number of replacements
system.cpu.l2cache.tags.tagsinuse 65291.754390 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 79532 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 787946 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 875689 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 43125 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 33706 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 76831 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 33710 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 33710 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 43125 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 67416 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 110541 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 305614500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 305848750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5531016720 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69544.544586 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69467.715128 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69521.586127 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 156621.714235 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 102365.809374 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 153666.360131 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153666.360131 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 59960.023188 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 155143.949508 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 118010.154603 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 21652739 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 21644705 # Transaction distribution
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 3006288 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 2043660850 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 470306 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 32992382 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.003506 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.059104 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 33102923 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.033230 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.179236 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 32876724 99.65% 99.65% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 115658 0.35% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 32002916 96.68% 96.68% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1100007 3.32% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 32992382 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 33102923 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 25622352750 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 1278000 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 14049088 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 173882714 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3324 # Total snoops (count)
-system.membus.snoop_fanout::samples 2750930 # Request fanout histogram
+system.membus.snoop_fanout::samples 2861471 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2750930 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2861471 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2750930 # Request fanout histogram
+system.membus.snoop_fanout::total 2861471 # Request fanout histogram
system.membus.reqLayer0.occupancy 107107000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
sim_ticks 51111152682000 # Number of ticks simulated
final_tick 51111152682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1095499 # Simulator instruction rate (inst/s)
-host_op_rate 1287391 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 56869697369 # Simulator tick rate (ticks/s)
-host_mem_usage 728040 # Number of bytes of host memory used
-host_seconds 898.74 # Real time elapsed on the host
+host_inst_rate 1028340 # Simulator instruction rate (inst/s)
+host_op_rate 1208468 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53383325140 # Simulator tick rate (ticks/s)
+host_mem_usage 714148 # Number of bytes of host memory used
+host_seconds 957.44 # Real time elapsed on the host
sim_insts 984570519 # Number of instructions simulated
sim_ops 1157031967 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size_system.iocache.mem_side::total 14217536 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 227116986 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 3583531 # Request fanout histogram
+system.membus.snoop_fanout::samples 3693816 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 3583531 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 3693816 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 3583531 # Request fanout histogram
+system.membus.snoop_fanout::total 3693816 # Request fanout histogram
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6620864 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2239440306 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 116338 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 36240472 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.003188 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.056369 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 36350757 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.037391 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.189718 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 36124951 99.68% 99.68% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 115521 0.32% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 34991565 96.26% 96.26% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 1359192 3.74% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 36240472 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 36350757 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 51274696167500 # Number of ticks simulated
final_tick 51274696167500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 281052 # Simulator instruction rate (inst/s)
-host_op_rate 330247 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16260391227 # Simulator tick rate (ticks/s)
-host_mem_usage 656704 # Number of bytes of host memory used
-host_seconds 3153.35 # Real time elapsed on the host
+host_inst_rate 293957 # Simulator instruction rate (inst/s)
+host_op_rate 345410 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17006997815 # Simulator tick rate (ticks/s)
+host_mem_usage 724900 # Number of bytes of host memory used
+host_seconds 3014.92 # Real time elapsed on the host
sim_insts 886256415 # Number of instructions simulated
sim_ops 1041383802 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.overall_mshr_misses::cpu1.data 1288838 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 3261967 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 4550805 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 10846992750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 30627833111 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 41474825861 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17677.220786 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19254.630415 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18807.890668 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164300.431351 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 178149.293514 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172652.928608 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 166593.057882 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 181697.568974 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 175590.522688 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 165438.799556 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 179883.665144 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174097.912607 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 14550991 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.976833 # Cycle average of tags in use
system.l2c.overall_mshr_misses::cpu2.inst 34248 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 279438 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 440923 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5448 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data 8279 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 13727 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5373 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data 7916 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 13289 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10821 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data 16195 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 27016 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 45139750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 44046000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 809585750 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73676.090575 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 85155.613786 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 79627.010818 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150300.018355 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 164140.053147 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 158647.191666 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 153591.103666 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 168686.141486 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 162582.925427 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151934.155808 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 166362.148564 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 160583.154279 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 465050 # Transaction distribution
system.membus.trans_dist::ReadResp 465050 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 14192960 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 173983314 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 541 # Total snoops (count)
-system.membus.snoop_fanout::samples 2749696 # Request fanout histogram
+system.membus.snoop_fanout::samples 2860073 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2749696 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2860073 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2749696 # Request fanout histogram
+system.membus.snoop_fanout::total 2860073 # Request fanout histogram
system.membus.reqLayer0.occupancy 47655000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1500 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6299696 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2099087298 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 376855 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 34241641 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.003374 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.057992 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 34352020 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.045142 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.207615 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 34126094 99.66% 99.66% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 115547 0.34% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 32801302 95.49% 95.49% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 1550718 4.51% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 34241641 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 34352020 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 13384646524 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 375000 # Layer occupancy (ticks)
sim_ticks 51318118168000 # Number of ticks simulated
final_tick 51318118168000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 135924 # Simulator instruction rate (inst/s)
-host_op_rate 159711 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 7679227340 # Simulator tick rate (ticks/s)
-host_mem_usage 666876 # Number of bytes of host memory used
-host_seconds 6682.72 # Real time elapsed on the host
+host_inst_rate 134879 # Simulator instruction rate (inst/s)
+host_op_rate 158483 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7620199718 # Simulator tick rate (ticks/s)
+host_mem_usage 732720 # Number of bytes of host memory used
+host_seconds 6734.48 # Real time elapsed on the host
sim_insts 908340493 # Number of instructions simulated
sim_ops 1067303522 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.overall_mshr_misses::cpu0.data 4712310 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 4585034 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 9297344 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16397 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 17283 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 33680 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17951 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 15746 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 33697 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34348 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 33029 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 67377 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 43556644701 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 43095096417 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 86651741118 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20069.856975 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20098.578829 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20084.021308 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 170531.469171 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171562.706127 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171060.651722 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157771.853156 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 176775.368792 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 166651.853073 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 163863.020729 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 174047.752187 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 168855.696202 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 16169102 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.955735 # Cycle average of tags in use
system.cpu0.icache.overall_mshr_misses::cpu0.inst 8013787 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 8155949 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 16169736 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 12341 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu1.inst 8298 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total 20639 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 12341 # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu1.inst 8298 # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total 20639 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 95968094429 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 97614087232 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 193582181661 # number of ReadReq MSHR miss cycles
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11975.373744 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11968.452381 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11971.882637 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.membus.trans_dist::ReadResp 483310 # Transaction distribution
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system.membus.pkt_size::total 188425258 # Cumulative packet size per connected master and slave (bytes)
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system.membus.snoop_fanout::mean 1 # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
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system.membus.reqLayer0.occupancy 113801500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 51156 # Layer occupancy (ticks)
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system.toL2Bus.snoops 669395 # Total snoops (count)
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system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
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system.toL2Bus.reqLayer0.occupancy 28102852815 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1161000 # Layer occupancy (ticks)
sim_ticks 51824540977500 # Number of ticks simulated
final_tick 51824540977500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 650287 # Simulator instruction rate (inst/s)
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.icache.tags.tagsinuse 511.880033 # Cycle average of tags in use
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 153666.449125 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 59879.454644 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 158677.272727 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60077.876955 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 151586.838737 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 118009.842502 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 450083 # Transaction distribution
system.membus.trans_dist::ReadResp 450083 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 14048000 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 174054362 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 3335 # Total snoops (count)
-system.membus.snoop_fanout::samples 2753479 # Request fanout histogram
+system.membus.snoop_fanout::samples 2864020 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2753479 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2864020 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2753479 # Request fanout histogram
+system.membus.snoop_fanout::total 2864020 # Request fanout histogram
system.membus.reqLayer0.occupancy 107121000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 41500 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 3951520 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 2057658738 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 492069 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 33406949 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.003462 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.058735 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 33517490 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.039407 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.194561 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 33291303 99.65% 99.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 115646 0.35% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 32196665 96.06% 96.06% # Request fanout histogram
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system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 33406949 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 33517490 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 25817690750 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 1207500 # Layer occupancy (ticks)
sim_ticks 5122212682000 # Number of ticks simulated
final_tick 5122212682000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 132606 # Simulator instruction rate (inst/s)
-host_op_rate 262116 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1665061517 # Simulator tick rate (ticks/s)
-host_mem_usage 804736 # Number of bytes of host memory used
-host_seconds 3076.29 # Real time elapsed on the host
+host_inst_rate 178126 # Simulator instruction rate (inst/s)
+host_op_rate 352092 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2236626113 # Simulator tick rate (ticks/s)
+host_mem_usage 810964 # Number of bytes of host memory used
+host_seconds 2290.15 # Real time elapsed on the host
sim_insts 407934867 # Number of instructions simulated
sim_ops 806343968 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 1259107 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1662065 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1662065 # number of overall MSHR misses
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+system.cpu.dcache.WriteReq_mshr_uncacheable::total 13919 # number of WriteReq MSHR uncacheable
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+system.cpu.dcache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 12834468768 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 12834468768 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12344104823 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 19997.167509 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 18735.342987 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 18735.342987 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 161161.122604 # average ReadReq mshr uncacheable latency
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+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186317.120483 # average WriteReq mshr uncacheable latency
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 161727.134590 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dtb_walker_cache.tags.replacements 77765 # number of replacements
system.cpu.dtb_walker_cache.tags.tagsinuse 13.263782 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 16361 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 169729 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 186163 # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 618620 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 618620 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 5264500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 578000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1161518218 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70993.106656 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 66722.858109 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67103.370176 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147161.069686 # average ReadReq mshr uncacheable latency
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+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173241.755873 # average WriteReq mshr uncacheable latency
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 147747.887233 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 3067430 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 3066889 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 288754 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 288754 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq 1643 # Transaction distribution
system.cpu.toL2Bus.trans_dist::BadAddressError 4 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1994880 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6121448 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 973632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5848896 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 278538304 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 61672 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4387054 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.010870 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.103692 # Request fanout histogram
+system.cpu.toL2Bus.snoops 63315 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5007317 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.009852 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4339366 98.91% 98.91% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4387054 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.occupancy 4072528967 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 555000 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 26225708 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1635 # Total snoops (count)
-system.membus.snoop_fanout::samples 385314 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
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+system.membus.snoop_fanout::mean 1.001634 # Request fanout histogram
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system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 385314 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 385314 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
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system.membus.reqLayer0.occupancy 357821000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 388531000 # Layer occupancy (ticks)
sim_ticks 5133731116500 # Number of ticks simulated
final_tick 5133731116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 201130 # Simulator instruction rate (inst/s)
-host_op_rate 399856 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4230291451 # Simulator tick rate (ticks/s)
-host_mem_usage 1019904 # Number of bytes of host memory used
-host_seconds 1213.56 # Real time elapsed on the host
+host_inst_rate 268887 # Simulator instruction rate (inst/s)
+host_op_rate 534560 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5655392824 # Simulator tick rate (ticks/s)
+host_mem_usage 1025452 # Number of bytes of host memory used
+host_seconds 907.76 # Real time elapsed on the host
sim_insts 244084329 # Number of instructions simulated
sim_ops 485251122 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.overall_mshr_misses::cpu1.data 287154 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 734585 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1021739 # number of overall MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable
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system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 1988518250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 5713340764 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7701859014 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18773.696132 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16498.435737 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17137.884876 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162092.138802 # average ReadReq mshr uncacheable latency
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+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 196782.670455 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 186073.497268 # average WriteReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 162531.827575 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 871419 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.241344 # Cycle average of tags in use
system.l2c.overall_mshr_misses::cpu2.inst 5224 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 49327 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 88886 # number of overall MSHR misses
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+system.l2c.WriteReq_mshr_uncacheable::cpu2.data 3872 # number of WriteReq MSHR uncacheable
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+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 190062 # number of overall MSHR uncacheable misses
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+system.l2c.overall_mshr_uncacheable_misses::total 399245 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 70000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 193782500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 330037250 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73703.244640 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 69123.677398 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 67612.992451 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 149115.529917 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 146883.437809 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147946.242266 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 160916.038283 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 183774.535124 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 173007.308743 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 149329.608233 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 147566.296018 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 148405.727060 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 5117226 # Transaction distribution
system.membus.trans_dist::ReadResp 5117226 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 6011648 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 33300229 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 820 # Total snoops (count)
-system.membus.snoop_fanout::samples 372049 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::samples 5455844 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.000311 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.017639 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 372049 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 5454146 99.97% 99.97% # Request fanout histogram
+system.membus.snoop_fanout::2 1698 0.03% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 372049 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
+system.membus.snoop_fanout::total 5455844 # Request fanout histogram
system.membus.reqLayer0.occupancy 234105000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 304102500 # Layer occupancy (ticks)
system.toL2Bus.trans_dist::UpgradeResp 1672 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 290026 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 290026 # Transaction distribution
+system.toL2Bus.trans_dist::MessageReq 1151 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1743864 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 14988008 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.port::system.l2c.cpu_side 73882 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.itb.walker.port::system.l2c.cpu_side 274152 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.port::system.l2c.cpu_side 823488 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 270293669 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 72565 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 4266300 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.011166 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.105077 # Request fanout histogram
+system.toL2Bus.snoops 74263 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 9350095 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.022573 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.148538 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 4218663 98.88% 98.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 47637 1.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 9139035 97.74% 97.74% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 211060 2.26% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 4266300 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 9350095 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2511915480 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 402000 # Layer occupancy (ticks)
sim_ticks 61594138500 # Number of ticks simulated
final_tick 61594138500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 196979 # Simulator instruction rate (inst/s)
-host_op_rate 197960 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 133911114 # Simulator tick rate (ticks/s)
-host_mem_usage 438496 # Number of bytes of host memory used
-host_seconds 459.96 # Real time elapsed on the host
+host_inst_rate 265976 # Simulator instruction rate (inst/s)
+host_op_rate 267300 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 180817037 # Simulator tick rate (ticks/s)
+host_mem_usage 446692 # Number of bytes of host memory used
+host_seconds 340.64 # Real time elapsed on the host
sim_insts 90602850 # Number of instructions simulated
sim_ops 91054081 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 121232128 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1894252 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 1894252 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1894252 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1894252 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1890392000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 3.1 # Layer utilization (%)
sim_ticks 58203290500 # Number of ticks simulated
final_tick 58203290500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98982 # Simulator instruction rate (inst/s)
-host_op_rate 99475 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 63595388 # Simulator tick rate (ticks/s)
-host_mem_usage 438244 # Number of bytes of host memory used
-host_seconds 915.21 # Real time elapsed on the host
+host_inst_rate 131910 # Simulator instruction rate (inst/s)
+host_op_rate 132567 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 84750962 # Simulator tick rate (ticks/s)
+host_mem_usage 445160 # Number of bytes of host memory used
+host_seconds 686.76 # Real time elapsed on the host
sim_insts 90589799 # Number of instructions simulated
sim_ops 91041030 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 698173056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 22116 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 10931068 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.002023 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.002023 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.044933 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 10908954 99.80% 99.80% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 22114 0.20% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 10908954 99.80% 99.80% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 22114 0.20% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 10931068 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10892444998 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 18.7 # Layer utilization (%)
sim_ticks 62108139000 # Number of ticks simulated
final_tick 62108139000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88749 # Simulator instruction rate (inst/s)
-host_op_rate 156272 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34888646 # Simulator tick rate (ticks/s)
-host_mem_usage 448856 # Number of bytes of host memory used
-host_seconds 1780.18 # Real time elapsed on the host
+host_inst_rate 114338 # Simulator instruction rate (inst/s)
+host_op_rate 201331 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 44948395 # Simulator tick rate (ticks/s)
+host_mem_usage 455560 # Number of bytes of host memory used
+host_seconds 1381.77 # Real time elapsed on the host
sim_insts 157988547 # Number of instructions simulated
sim_ops 278192464 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 265234496 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4144289 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4144289 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 4144289 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 4144289 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4138867500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 6.7 # Layer utilization (%)
sim_ticks 365989065500 # Number of ticks simulated
final_tick 365989065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 638452 # Simulator instruction rate (inst/s)
-host_op_rate 1124211 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1479007835 # Simulator tick rate (ticks/s)
-host_mem_usage 450980 # Number of bytes of host memory used
-host_seconds 247.46 # Real time elapsed on the host
+host_inst_rate 678113 # Simulator instruction rate (inst/s)
+host_op_rate 1194048 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1570885616 # Simulator tick rate (ticks/s)
+host_mem_usage 451452 # Number of bytes of host memory used
+host_seconds 232.98 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 264327744 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4130121 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4130121 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 4130121 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 4130121 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4127544500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
sim_ticks 366339500500 # Number of ticks simulated
final_tick 366339500500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 174606 # Simulator instruction rate (inst/s)
-host_op_rate 189122 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 126268215 # Simulator tick rate (ticks/s)
-host_mem_usage 309684 # Number of bytes of host memory used
-host_seconds 2901.28 # Real time elapsed on the host
+host_inst_rate 237525 # Simulator instruction rate (inst/s)
+host_op_rate 257271 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 171768388 # Simulator tick rate (ticks/s)
+host_mem_usage 317860 # Number of bytes of host memory used
+host_seconds 2132.75 # Real time elapsed on the host
sim_insts 506582156 # Number of instructions simulated
sim_ops 548695379 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 142850048 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2232032 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 2232032 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 2232032 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2232032 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2184563000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
sim_ticks 233457400500 # Number of ticks simulated
final_tick 233457400500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 105147 # Simulator instruction rate (inst/s)
-host_op_rate 113911 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48585649 # Simulator tick rate (ticks/s)
-host_mem_usage 312624 # Number of bytes of host memory used
-host_seconds 4805.07 # Real time elapsed on the host
+host_inst_rate 140578 # Simulator instruction rate (inst/s)
+host_op_rate 152296 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 64957541 # Simulator tick rate (ticks/s)
+host_mem_usage 319412 # Number of bytes of host memory used
+host_seconds 3594.00 # Real time elapsed on the host
sim_insts 505237724 # Number of instructions simulated
sim_ops 547350945 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 335917632 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 317126 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 5565869 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.056971 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.056971 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.231787 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 5248777 94.30% 94.30% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 317092 5.70% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5248777 94.30% 94.30% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 317092 5.70% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 5565869 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4977148500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
sim_ticks 279362298000 # Number of ticks simulated
final_tick 279362298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1382525 # Simulator instruction rate (inst/s)
-host_op_rate 1497457 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 762414599 # Simulator tick rate (ticks/s)
-host_mem_usage 298924 # Number of bytes of host memory used
-host_seconds 366.42 # Real time elapsed on the host
+host_inst_rate 1944100 # Simulator instruction rate (inst/s)
+host_op_rate 2105717 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1072104103 # Simulator tick rate (ticks/s)
+host_mem_usage 306580 # Number of bytes of host memory used
+host_seconds 260.57 # Real time elapsed on the host
sim_insts 506581608 # Number of instructions simulated
sim_ops 548694829 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 2705365829 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 687930750 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.750964 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.750964 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.432455 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 171319374 24.90% 24.90% # Request fanout histogram
-system.membus.snoop_fanout::3 516611376 75.10% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 171319374 24.90% 24.90% # Request fanout histogram
+system.membus.snoop_fanout::1 516611376 75.10% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 687930750 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 141782016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 2215344 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 2215344 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 2215344 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 2215344 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2172577000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
---------- Begin Simulation Statistics ----------
-sim_seconds 0.417785 # Number of seconds simulated
-sim_ticks 417784645500 # Number of ticks simulated
-final_tick 417784645500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.417996 # Number of seconds simulated
+sim_ticks 417996021500 # Number of ticks simulated
+final_tick 417996021500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 77548 # Simulator instruction rate (inst/s)
-host_op_rate 143396 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39181823 # Simulator tick rate (ticks/s)
-host_mem_usage 423644 # Number of bytes of host memory used
-host_seconds 10662.72 # Real time elapsed on the host
+host_inst_rate 98610 # Simulator instruction rate (inst/s)
+host_op_rate 182341 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 49848381 # Simulator tick rate (ticks/s)
+host_mem_usage 430328 # Number of bytes of host memory used
+host_seconds 8385.35 # Real time elapsed on the host
sim_insts 826877109 # Number of instructions simulated
sim_ops 1528988701 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 225536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 227200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 24536320 # Number of bytes read from this memory
-system.physmem.bytes_read::total 24761856 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 225536 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 225536 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 18818176 # Number of bytes written to this memory
-system.physmem.bytes_written::total 18818176 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3524 # Number of read requests responded to by this memory
+system.physmem.bytes_read::total 24763520 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 227200 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 227200 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 18818240 # Number of bytes written to this memory
+system.physmem.bytes_written::total 18818240 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.inst 3550 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 383380 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 386904 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 294034 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 294034 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 539838 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 58729588 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 59269426 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 539838 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 539838 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 45042766 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 45042766 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 45042766 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 539838 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 58729588 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 104312192 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 386904 # Number of read requests accepted
-system.physmem.writeReqs 294034 # Number of write requests accepted
-system.physmem.readBursts 386904 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 294034 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 24739840 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 22016 # Total number of bytes read from write queue
-system.physmem.bytesWritten 18816320 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 24761856 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 18818176 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 344 # Number of DRAM read bursts serviced by the write queue
+system.physmem.num_reads::total 386930 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 294035 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 294035 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.inst 543546 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 58699889 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 59243435 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 543546 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 543546 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 45020141 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 45020141 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 45020141 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 543546 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 58699889 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 104263576 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 386930 # Number of read requests accepted
+system.physmem.writeReqs 294035 # Number of write requests accepted
+system.physmem.readBursts 386930 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 294035 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 24740928 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 22592 # Total number of bytes read from write queue
+system.physmem.bytesWritten 18817024 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 24763520 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 18818240 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 353 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 194832 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 24113 # Per bank write bursts
-system.physmem.perBankRdBursts::1 26506 # Per bank write bursts
-system.physmem.perBankRdBursts::2 24704 # Per bank write bursts
-system.physmem.perBankRdBursts::3 24585 # Per bank write bursts
-system.physmem.perBankRdBursts::4 23284 # Per bank write bursts
-system.physmem.perBankRdBursts::5 23758 # Per bank write bursts
-system.physmem.perBankRdBursts::6 24455 # Per bank write bursts
-system.physmem.perBankRdBursts::7 24304 # Per bank write bursts
-system.physmem.perBankRdBursts::8 23622 # Per bank write bursts
-system.physmem.perBankRdBursts::9 23951 # Per bank write bursts
-system.physmem.perBankRdBursts::10 24786 # Per bank write bursts
-system.physmem.perBankRdBursts::11 24077 # Per bank write bursts
-system.physmem.perBankRdBursts::12 23364 # Per bank write bursts
-system.physmem.perBankRdBursts::13 22990 # Per bank write bursts
-system.physmem.perBankRdBursts::14 24090 # Per bank write bursts
-system.physmem.perBankRdBursts::15 23971 # Per bank write bursts
-system.physmem.perBankWrBursts::0 18545 # Per bank write bursts
-system.physmem.perBankWrBursts::1 19845 # Per bank write bursts
-system.physmem.perBankWrBursts::2 18943 # Per bank write bursts
-system.physmem.perBankWrBursts::3 18938 # Per bank write bursts
-system.physmem.perBankWrBursts::4 18040 # Per bank write bursts
-system.physmem.perBankWrBursts::5 18456 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 195133 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 24110 # Per bank write bursts
+system.physmem.perBankRdBursts::1 26511 # Per bank write bursts
+system.physmem.perBankRdBursts::2 24689 # Per bank write bursts
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+system.physmem.perBankRdBursts::4 23301 # Per bank write bursts
+system.physmem.perBankRdBursts::5 23773 # Per bank write bursts
+system.physmem.perBankRdBursts::6 24463 # Per bank write bursts
+system.physmem.perBankRdBursts::7 24300 # Per bank write bursts
+system.physmem.perBankRdBursts::8 23625 # Per bank write bursts
+system.physmem.perBankRdBursts::9 23952 # Per bank write bursts
+system.physmem.perBankRdBursts::10 24787 # Per bank write bursts
+system.physmem.perBankRdBursts::11 24070 # Per bank write bursts
+system.physmem.perBankRdBursts::12 23353 # Per bank write bursts
+system.physmem.perBankRdBursts::13 22981 # Per bank write bursts
+system.physmem.perBankRdBursts::14 24097 # Per bank write bursts
+system.physmem.perBankRdBursts::15 23979 # Per bank write bursts
+system.physmem.perBankWrBursts::0 18543 # Per bank write bursts
+system.physmem.perBankWrBursts::1 19847 # Per bank write bursts
+system.physmem.perBankWrBursts::2 18947 # Per bank write bursts
+system.physmem.perBankWrBursts::3 18939 # Per bank write bursts
+system.physmem.perBankWrBursts::4 18047 # Per bank write bursts
+system.physmem.perBankWrBursts::5 18457 # Per bank write bursts
system.physmem.perBankWrBursts::6 18996 # Per bank write bursts
-system.physmem.perBankWrBursts::7 18987 # Per bank write bursts
-system.physmem.perBankWrBursts::8 18549 # Per bank write bursts
-system.physmem.perBankWrBursts::9 18172 # Per bank write bursts
-system.physmem.perBankWrBursts::10 18834 # Per bank write bursts
-system.physmem.perBankWrBursts::11 17732 # Per bank write bursts
-system.physmem.perBankWrBursts::12 17374 # Per bank write bursts
-system.physmem.perBankWrBursts::13 16972 # Per bank write bursts
+system.physmem.perBankWrBursts::7 18981 # Per bank write bursts
+system.physmem.perBankWrBursts::8 18548 # Per bank write bursts
+system.physmem.perBankWrBursts::9 18168 # Per bank write bursts
+system.physmem.perBankWrBursts::10 18839 # Per bank write bursts
+system.physmem.perBankWrBursts::11 17728 # Per bank write bursts
+system.physmem.perBankWrBursts::12 17372 # Per bank write bursts
+system.physmem.perBankWrBursts::13 16973 # Per bank write bursts
system.physmem.perBankWrBursts::14 17820 # Per bank write bursts
-system.physmem.perBankWrBursts::15 17802 # Per bank write bursts
+system.physmem.perBankWrBursts::15 17811 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 417784619000 # Total gap between requests
+system.physmem.totGap 417995980500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 386904 # Read request sizes (log2)
+system.physmem.readPktSize::6 386930 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 294034 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 381510 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 4656 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 343 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 42 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 8 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 294035 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 381501 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 4668 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 352 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 43 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 6151 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 6574 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 16911 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 17474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 17558 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 17562 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 17584 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 17583 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 17630 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 17652 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 17624 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 17632 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 17742 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 17647 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 17645 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 17830 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 17528 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 17474 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 39 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 27 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 21 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 15 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 10 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 6 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 7 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 17825 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 17527 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::33 34 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 147384 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 295.518428 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.412890 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 322.590500 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 54886 37.24% 37.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 39792 27.00% 64.24% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 13719 9.31% 73.55% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 7560 5.13% 78.68% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 5573 3.78% 82.46% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 3862 2.62% 85.08% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 3103 2.11% 87.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 2674 1.81% 89.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 16215 11.00% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 147384 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 17444 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 22.159252 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 209.918601 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 17431 99.93% 99.93% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 147449 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 295.402912 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.387317 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 322.474139 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 54872 37.21% 37.21% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 39881 27.05% 64.26% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 13729 9.31% 73.57% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 7544 5.12% 78.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 5538 3.76% 82.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 3897 2.64% 85.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 3110 2.11% 87.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 2694 1.83% 89.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 16184 10.98% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 147449 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 17448 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 22.155834 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 209.387263 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 17435 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 8 0.05% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 3 0.02% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::26624-27647 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 17444 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 17444 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 16.854219 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 16.780353 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 2.660093 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 17244 98.85% 98.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 141 0.81% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 26 0.15% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 11 0.06% 99.87% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 17448 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 17448 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 16.850986 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 16.777295 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 2.658929 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 17245 98.84% 98.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 147 0.84% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 24 0.14% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 10 0.06% 99.87% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 5 0.03% 99.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 3 0.02% 99.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 3 0.02% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::104-107 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::236-239 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 17444 # Writes before turning the bus around for reads
-system.physmem.totQLat 4274781750 # Total ticks spent queuing
-system.physmem.totMemAccLat 11522781750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1932800000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11058.52 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 17448 # Writes before turning the bus around for reads
+system.physmem.totQLat 4282714250 # Total ticks spent queuing
+system.physmem.totMemAccLat 11531033000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1932885000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 11078.55 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 29808.52 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 59.22 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 45.04 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 59.27 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 45.04 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 29828.55 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 59.19 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 45.02 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 59.24 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 45.02 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.81 # Data bus utilization in percentage
system.physmem.busUtilRead 0.46 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.35 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.29 # Average write queue length when enqueuing
-system.physmem.readRowHits 318043 # Number of row buffer hits during reads
-system.physmem.writeRowHits 215127 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.28 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.16 # Row buffer hit rate for writes
-system.physmem.avgGap 613542.82 # Average gap between requests
-system.physmem.pageHitRate 78.34 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 567476280 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 309634875 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 1526389800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 976691520 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 63728995635 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 194764938000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 289161421470 # Total energy per rank (pJ)
-system.physmem_0.averagePower 692.139218 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 323446024000 # Time in different power states
-system.physmem_0.memoryStateTime::REF 13950560000 # Time in different power states
+system.physmem.avgWrQLen 21.74 # Average write queue length when enqueuing
+system.physmem.readRowHits 318033 # Number of row buffer hits during reads
+system.physmem.writeRowHits 215097 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.27 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.15 # Row buffer hit rate for writes
+system.physmem.avgGap 613828.88 # Average gap between requests
+system.physmem.pageHitRate 78.33 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 567967680 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 309903000 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 1526584800 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 976607280 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 63862686000 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 194773803000 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 289318578240 # Total energy per rank (pJ)
+system.physmem_0.averagePower 692.167087 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 323459791500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 13957580000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 80384174500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 80574068000 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 546399000 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 298134375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1488177600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 928104480 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 27287295360 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 61807042845 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 196450861500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 288806015160 # Total energy per rank (pJ)
-system.physmem_1.averagePower 691.288514 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 326265955250 # Time in different power states
-system.physmem_1.memoryStateTime::REF 13950560000 # Time in different power states
+system.physmem_1.actEnergy 546278040 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 298068375 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 1488138600 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 928098000 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 27301026480 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 61813739205 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 196571124750 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 288946473450 # Total energy per rank (pJ)
+system.physmem_1.averagePower 691.276862 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 326467583000 # Time in different power states
+system.physmem_1.memoryStateTime::REF 13957580000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 77563900250 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 77566206500 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 230228501 # Number of BP lookups
-system.cpu.branchPred.condPredicted 230228501 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 9739021 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 131459692 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 128773186 # Number of BTB hits
+system.cpu.branchPred.lookups 230262495 # Number of BP lookups
+system.cpu.branchPred.condPredicted 230262495 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 9742888 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 131521089 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 128797905 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.956403 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 27739164 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1472550 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 97.929470 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 27751403 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1472504 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
-system.cpu.numCycles 835569292 # number of cpu cycles simulated
+system.cpu.numCycles 835992044 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 185184379 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1269166320 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 230228501 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 156512350 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 639147953 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 20213743 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 511 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.MiscStallCycles 99253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 822297 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 1772 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 179484418 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 2740851 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.icacheStallCycles 185232757 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1269385486 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 230262495 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 156549308 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 639500926 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 20224879 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 485 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.MiscStallCycles 100878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 834249 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 1640 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 42 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 179526470 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 2741098 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 7 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 835363066 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 2.826562 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.382493 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 835783416 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 2.825648 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.381813 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 427868247 51.22% 51.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 33702021 4.03% 55.25% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 32929710 3.94% 59.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 33265996 3.98% 63.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 27012416 3.23% 66.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 27748723 3.32% 69.73% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 36992796 4.43% 74.16% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 33648824 4.03% 78.19% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 182194333 21.81% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 428043161 51.21% 51.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 33828750 4.05% 55.26% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 32944896 3.94% 59.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 33232373 3.98% 63.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 27262474 3.26% 66.44% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 27644327 3.31% 69.75% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 36950250 4.42% 74.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 33776724 4.04% 78.21% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 182100461 21.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 835363066 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.275535 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.518924 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 127510375 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 375947418 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 240571925 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 81226477 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 10106871 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 2225382694 # Number of instructions handled by decode
-system.cpu.rename.SquashCycles 10106871 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 159640008 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 160513488 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 42854 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 285557624 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 219502221 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 2175351414 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 185986 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 136028392 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 24255750 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 49096014 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 2279465980 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5501874168 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 3499442561 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 66867 # Number of floating rename lookups
+system.cpu.fetch.rateDist::total 835783416 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.275436 # Number of branch fetches per cycle
+system.cpu.fetch.rate 1.518418 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 127710765 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 376117098 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 240273770 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 81569344 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 10112439 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 2225700133 # Number of instructions handled by decode
+system.cpu.rename.SquashCycles 10112439 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 159685424 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 160601450 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 42674 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 285796855 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 219544574 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 2175664077 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 185857 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 136149821 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LQFullEvents 24262583 # Number of times rename has blocked due to LQ full
+system.cpu.rename.SQFullEvents 49140413 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 2279803570 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5502723498 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 3499975195 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 67752 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1614040854 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 665425126 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 3167 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2999 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 415602419 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 528341229 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 209838821 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 239501304 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 72157646 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 2101036293 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 25395 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1826926557 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 429463 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 572072987 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 974001425 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 24843 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 835363066 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 2.186985 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.073368 # Number of insts issued each cycle
+system.cpu.rename.UndoneMaps 665762716 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 3202 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 3008 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 414696821 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 528426075 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 209872279 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 239265917 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 72168406 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 2101339198 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 25266 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 1827025844 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 429417 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 572375763 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 974716036 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 24714 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 835783416 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 2.186004 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.072692 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 255962202 30.64% 30.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 125607638 15.04% 45.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 118770145 14.22% 59.89% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 111086257 13.30% 73.19% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 92824001 11.11% 84.30% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 61460839 7.36% 91.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 43056890 5.15% 96.82% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 19182433 2.30% 99.11% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 7412661 0.89% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 256113706 30.64% 30.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 125601677 15.03% 45.67% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 119268677 14.27% 59.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 111065913 13.29% 73.23% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 92467369 11.06% 84.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 61706105 7.38% 91.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 43038473 5.15% 96.83% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 19113733 2.29% 99.11% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 7407763 0.89% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 835363066 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 835783416 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 11317596 42.46% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.46% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 12272214 46.05% 88.51% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 3062486 11.49% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 11312018 42.37% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 42.37% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 12328079 46.18% 88.55% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 3055344 11.45% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2719434 0.15% 0.15% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 1211207278 66.30% 66.45% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 389699 0.02% 66.47% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 3880989 0.21% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 135 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 2717945 0.15% 0.15% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 1211291441 66.30% 66.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 390219 0.02% 66.47% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 3881058 0.21% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 119 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 39 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 410 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 36 0.00% 66.68% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 409 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 435021653 23.81% 90.49% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 173706920 9.51% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 435052343 23.81% 90.49% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 173692274 9.51% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1826926557 # Type of FU issued
-system.cpu.iq.rate 2.186445 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 26652296 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.014589 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 4516265766 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 2673396604 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 1796798251 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 32173 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 70520 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 7153 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1850844448 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 14971 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 185549711 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 1827025844 # Type of FU issued
+system.cpu.iq.rate 2.185458 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 26695441 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.014611 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 4516927324 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 2674001021 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 1796885315 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 32638 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 71794 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 7253 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 1850988135 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 15205 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 185719617 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 144242393 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 210251 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 386532 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 60678635 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 144326663 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 210089 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 386690 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 60712093 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 19153 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 1029 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 19150 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 1058 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 10106871 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 107291908 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 6438859 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 2101061688 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 392799 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 528344550 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 209838821 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 7385 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1906737 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3653179 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 386532 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 5738958 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 4581595 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 10320553 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 1805492449 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 428838978 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 21434108 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 10112439 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 107482997 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 6407343 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 2101364464 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 396756 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 528428820 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 209872279 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 7401 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1872023 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3639843 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 386690 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 5742846 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 4583278 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 10326124 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 1805593119 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 428868135 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 21432725 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 598981338 # number of memory reference insts executed
-system.cpu.iew.exec_branches 171787473 # Number of branches executed
-system.cpu.iew.exec_stores 170142360 # Number of stores executed
-system.cpu.iew.exec_rate 2.160793 # Inst execution rate
-system.cpu.iew.wb_sent 1802094257 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 1796805404 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 1368063103 # num instructions producing a value
-system.cpu.iew.wb_consumers 2090238527 # num instructions consuming a value
+system.cpu.iew.exec_refs 598999412 # number of memory reference insts executed
+system.cpu.iew.exec_branches 171793179 # Number of branches executed
+system.cpu.iew.exec_stores 170131277 # Number of stores executed
+system.cpu.iew.exec_rate 2.159821 # Inst execution rate
+system.cpu.iew.wb_sent 1802187162 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 1796892568 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 1367992688 # num instructions producing a value
+system.cpu.iew.wb_consumers 2090178306 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 2.150397 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.654501 # average fanout of values written-back
+system.cpu.iew.wb_rate 2.149413 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.654486 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 572152437 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 572454923 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 552 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 9826757 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 757699482 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 2.017936 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.547497 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 9832210 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 758082487 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 2.016916 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 2.546878 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 289066041 38.15% 38.15% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 175144894 23.12% 61.27% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 57411271 7.58% 68.84% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 86235215 11.38% 80.22% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 27150149 3.58% 83.81% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 27136057 3.58% 87.39% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 9784065 1.29% 88.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 8843971 1.17% 89.85% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 76927819 10.15% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 289327383 38.17% 38.17% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 175257093 23.12% 61.28% # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedInsts 826877109 # Number of instructions committed
system.cpu.commit.committedOps 1528988701 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total 1528988701 # Class of committed instruction
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-system.cpu.idleCycles 206226 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.committedInsts 826877109 # Number of Instructions Simulated
system.cpu.committedOps 1528988701 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 1.010512 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.010512 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.989597 # IPC: Total IPC of All Threads
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system.cpu.misc_regfile_writes 1 # number of misc regfile writes
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system.cpu.dcache.tags.warmup_cycle 1688557250 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.overall_mshr_miss_rate::total 0.151924 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70439.312870 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 68414.858277 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 68454.807142 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18051.645277 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18051.645277 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66860.724177 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66860.724177 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70439.312870 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67575.740087 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67602.017575 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 1972322 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 1972321 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 2332976 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 196692 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 196692 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 771484 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 771484 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214105 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803050 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8017155 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 553216 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311764544 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 312317760 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 196816 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 5273474 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.trans_dist::ReadReq 1972695 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 1972693 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 2332980 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 196977 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 196977 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 771524 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 771524 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 214584 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 7803688 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8018272 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 559488 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 311766848 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 312326336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 197098 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 5274176 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 5273474 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 5274176 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 5273474 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4998709391 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 5274176 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4998685151 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 308726995 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 309293990 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3988953025 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3989146355 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 179934 # Transaction distribution
-system.membus.trans_dist::ReadResp 179934 # Transaction distribution
-system.membus.trans_dist::Writeback 294034 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 194832 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 194832 # Transaction distribution
-system.membus.trans_dist::ReadExReq 206970 # Transaction distribution
-system.membus.trans_dist::ReadExResp 206970 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1457506 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1457506 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1457506 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43580032 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43580032 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 43580032 # Cumulative packet size per connected master and slave (bytes)
+system.membus.trans_dist::ReadReq 179950 # Transaction distribution
+system.membus.trans_dist::ReadResp 179949 # Transaction distribution
+system.membus.trans_dist::Writeback 294035 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 195133 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 195133 # Transaction distribution
+system.membus.trans_dist::ReadExReq 206980 # Transaction distribution
+system.membus.trans_dist::ReadExResp 206980 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1458160 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1458160 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1458160 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 43581696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 43581696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 43581696 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 875770 # Request fanout histogram
+system.membus.snoop_fanout::samples 876098 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 875770 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 876098 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 875770 # Request fanout histogram
-system.membus.reqLayer0.occupancy 2246779030 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 876098 # Request fanout histogram
+system.membus.reqLayer0.occupancy 2246796268 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2437213959 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 2437948408 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.6 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 885229328000 # Number of ticks simulated
final_tick 885229328000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1229934 # Simulator instruction rate (inst/s)
-host_op_rate 2274285 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1316729165 # Simulator tick rate (ticks/s)
-host_mem_usage 308776 # Number of bytes of host memory used
-host_seconds 672.29 # Real time elapsed on the host
+host_inst_rate 1361574 # Simulator instruction rate (inst/s)
+host_op_rate 2517703 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1457659146 # Simulator tick rate (ticks/s)
+host_mem_usage 313840 # Number of bytes of host memory used
+host_seconds 607.30 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 9654872754 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3702436212 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13357308966 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
-system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
-system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
-system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.667046 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 533262388 33.30% 33.30% # Request fanout histogram
-system.membus.snoop_fanout::3 1068347065 66.70% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 1528988702 # Class of executed instruction
+system.membus.trans_dist::ReadReq 1452449251 # Transaction distribution
+system.membus.trans_dist::ReadResp 1452449251 # Transaction distribution
+system.membus.trans_dist::WriteReq 149160202 # Transaction distribution
+system.membus.trans_dist::WriteResp 149160202 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 2136694130 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 2136694130 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1066524776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 1066524776 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 3203218906 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 8546776520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 8546776520 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 3277505120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 3277505120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 11824281640 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 1601609453 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.667046 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.471270 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 533262388 33.30% 33.30% # Request fanout histogram
+system.membus.snoop_fanout::1 1068347065 66.70% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 1601609453 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 1647872738500 # Number of ticks simulated
final_tick 1647872738500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 730118 # Simulator instruction rate (inst/s)
-host_op_rate 1350071 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1455043701 # Simulator tick rate (ticks/s)
-host_mem_usage 323120 # Number of bytes of host memory used
-host_seconds 1132.52 # Real time elapsed on the host
+host_inst_rate 720688 # Simulator instruction rate (inst/s)
+host_op_rate 1332632 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1436248802 # Simulator tick rate (ticks/s)
+host_mem_usage 323576 # Number of bytes of host memory used
+host_seconds 1147.35 # Real time elapsed on the host
sim_insts 826877110 # Number of instructions simulated
sim_ops 1528988702 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 310066880 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4844795 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4844795 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 4844795 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 4844795 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 4745920500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%)
sim_ticks 216744260000 # Number of ticks simulated
final_tick 216744260000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 123383 # Simulator instruction rate (inst/s)
-host_op_rate 148134 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 97944157 # Simulator tick rate (ticks/s)
-host_mem_usage 314844 # Number of bytes of host memory used
-host_seconds 2212.94 # Real time elapsed on the host
+host_inst_rate 172626 # Simulator instruction rate (inst/s)
+host_op_rate 207257 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 137034779 # Simulator tick rate (ticks/s)
+host_mem_usage 322768 # Number of bytes of host memory used
+host_seconds 1581.67 # Real time elapsed on the host
sim_insts 273037857 # Number of instructions simulated
sim_ops 327812214 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 2840064 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 44377 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 44377 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 44377 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 44377 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 23198500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
sim_ticks 112556618500 # Number of ticks simulated
final_tick 112556618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 95501 # Simulator instruction rate (inst/s)
-host_op_rate 114659 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 39369115 # Simulator tick rate (ticks/s)
-host_mem_usage 319836 # Number of bytes of host memory used
-host_seconds 2859.01 # Real time elapsed on the host
+host_inst_rate 125639 # Simulator instruction rate (inst/s)
+host_op_rate 150843 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 51793233 # Simulator tick rate (ticks/s)
+host_mem_usage 327772 # Number of bytes of host memory used
+host_seconds 2173.19 # Real time elapsed on the host
sim_insts 273037220 # Number of instructions simulated
sim_ops 327811602 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 205825792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 32515 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 3248545 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.009730 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.009730 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.098161 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3216936 99.03% 99.03% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 31609 0.97% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3216936 99.03% 99.03% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 31609 0.97% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 3248545 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2574809000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.3 # Layer utilization (%)
sim_ticks 201717314000 # Number of ticks simulated
final_tick 201717314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 854590 # Simulator instruction rate (inst/s)
-host_op_rate 1026030 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 631341281 # Simulator tick rate (ticks/s)
-host_mem_usage 304088 # Number of bytes of host memory used
-host_seconds 319.51 # Real time elapsed on the host
+host_inst_rate 1265309 # Simulator instruction rate (inst/s)
+host_op_rate 1519144 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 934796791 # Simulator tick rate (ticks/s)
+host_mem_usage 311752 # Number of bytes of host memory used
+host_seconds 215.79 # Real time elapsed on the host
sim_insts 273037595 # Number of instructions simulated
sim_ops 327811950 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 2275398075 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 517024352 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.674359 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.674359 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.468614 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 168364078 32.56% 32.56% # Request fanout histogram
-system.membus.snoop_fanout::3 348660274 67.44% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 168364078 32.56% 32.56% # Request fanout histogram
+system.membus.snoop_fanout::1 348660274 67.44% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 517024352 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 1349056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 21079 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 21079 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 21079 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 21079 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 11537500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
sim_ticks 545048444500 # Number of ticks simulated
final_tick 545048444500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 131789 # Simulator instruction rate (inst/s)
-host_op_rate 162250 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 112122004 # Simulator tick rate (ticks/s)
-host_mem_usage 314432 # Number of bytes of host memory used
-host_seconds 4861.21 # Real time elapsed on the host
+host_inst_rate 177094 # Simulator instruction rate (inst/s)
+host_op_rate 218026 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 150665678 # Simulator tick rate (ticks/s)
+host_mem_usage 323140 # Number of bytes of host memory used
+host_seconds 3617.60 # Real time elapsed on the host
sim_insts 640655085 # Number of instructions simulated
sim_ops 788730744 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 57537024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 899017 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 899017 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 899017 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 899017 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 540928500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
---------- Begin Simulation Statistics ----------
sim_seconds 0.409388 # Number of seconds simulated
-sim_ticks 409388341000 # Number of ticks simulated
-final_tick 409388341000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 409388416000 # Number of ticks simulated
+final_tick 409388416000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 75979 # Simulator instruction rate (inst/s)
-host_op_rate 93540 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48552243 # Simulator tick rate (ticks/s)
-host_mem_usage 312124 # Number of bytes of host memory used
-host_seconds 8431.91 # Real time elapsed on the host
+host_inst_rate 93306 # Simulator instruction rate (inst/s)
+host_op_rate 114872 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59624294 # Simulator tick rate (ticks/s)
+host_mem_usage 320320 # Number of bytes of host memory used
+host_seconds 6866.13 # Real time elapsed on the host
sim_insts 640649299 # Number of instructions simulated
sim_ops 788724958 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu.inst 226496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 226560 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 7024000 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher 12938624 # Number of bytes read from this memory
-system.physmem.bytes_read::total 20189120 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 226496 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 226496 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total 20189184 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 226560 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 226560 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 4245888 # Number of bytes written to this memory
system.physmem.bytes_written::total 4245888 # Number of bytes written to this memory
-system.physmem.num_reads::cpu.inst 3539 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 3540 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 109750 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher 202166 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 315455 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 315456 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 66342 # Number of write requests responded to by this memory
system.physmem.num_writes::total 66342 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu.inst 553255 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 17157303 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.l2cache.prefetcher 31604769 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 49315327 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 553255 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 553255 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 10371297 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 10371297 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 10371297 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 553255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 17157303 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.l2cache.prefetcher 31604769 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 59686624 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 315455 # Number of read requests accepted
+system.physmem.bw_read::cpu.inst 553411 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 17157300 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.l2cache.prefetcher 31604763 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 49315475 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 553411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 553411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 10371295 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 10371295 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 10371295 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 553411 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 17157300 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.l2cache.prefetcher 31604763 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 59686769 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 315456 # Number of read requests accepted
system.physmem.writeReqs 66342 # Number of write requests accepted
-system.physmem.readBursts 315455 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.readBursts 315456 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 66342 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 20169536 # Total number of bytes read from DRAM
+system.physmem.bytesReadDRAM 20169600 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 19584 # Total number of bytes read from write queue
system.physmem.bytesWritten 4238784 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 20189120 # Total read bytes from the system interface side
+system.physmem.bytesReadSys 20189184 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 4245888 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 306 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 81 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 18 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 19 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 19899 # Per bank write bursts
system.physmem.perBankRdBursts::1 19575 # Per bank write bursts
system.physmem.perBankRdBursts::2 19715 # Per bank write bursts
system.physmem.perBankRdBursts::12 19604 # Per bank write bursts
system.physmem.perBankRdBursts::13 19959 # Per bank write bursts
system.physmem.perBankRdBursts::14 19457 # Per bank write bursts
-system.physmem.perBankRdBursts::15 19977 # Per bank write bursts
+system.physmem.perBankRdBursts::15 19978 # Per bank write bursts
system.physmem.perBankWrBursts::0 4260 # Per bank write bursts
system.physmem.perBankWrBursts::1 4107 # Per bank write bursts
system.physmem.perBankWrBursts::2 4142 # Per bank write bursts
system.physmem.perBankWrBursts::15 4150 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 409388286500 # Total gap between requests
+system.physmem.totGap 409388361500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 315455 # Read request sizes (log2)
+system.physmem.readPktSize::6 315456 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 66342 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 122393 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 122394 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 117234 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 14139 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 6795 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 136711 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 178.525503 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 128.653130 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 198.190580 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 136710 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 178.527277 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 128.653997 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 198.191580 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 54126 39.59% 39.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 57416 42.00% 81.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 14736 10.78% 92.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 57414 42.00% 81.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 14737 10.78% 92.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 1353 0.99% 93.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1490 1.09% 94.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1455 1.06% 95.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1216 0.89% 96.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1169 0.86% 97.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 3750 2.74% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 136711 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 136710 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 4038 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 65.701585 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::gmean 34.708310 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::28 2 0.05% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::31 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 4038 # Writes before turning the bus around for reads
-system.physmem.totQLat 9474891317 # Total ticks spent queuing
-system.physmem.totMemAccLat 15383935067 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1575745000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 30064.80 # Average queueing delay per DRAM burst
+system.physmem.totQLat 9474850817 # Total ticks spent queuing
+system.physmem.totMemAccLat 15383913317 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1575750000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 30064.58 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48814.80 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 48814.58 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 49.27 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 10.35 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 49.32 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.08 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.70 # Average write queue length when enqueuing
-system.physmem.readRowHits 218193 # Number of row buffer hits during reads
+system.physmem.readRowHits 218195 # Number of row buffer hits during reads
system.physmem.writeRowHits 26465 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 69.23 # Row buffer hit rate for reads
+system.physmem.readRowHitRate 69.24 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 39.94 # Row buffer hit rate for writes
-system.physmem.avgGap 1072266.90 # Average gap between requests
+system.physmem.avgGap 1072264.29 # Average gap between requests
system.physmem.pageHitRate 64.15 # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy 518729400 # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy 283036875 # Energy for precharge commands per rank (pJ)
system.physmem_0.preBackEnergy 161092645500 # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy 286455220215 # Total energy per rank (pJ)
system.physmem_0.averagePower 699.719632 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 267357168520 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 267357262270 # Time in different power states
system.physmem_0.memoryStateTime::REF 13670280000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_0.memoryStateTime::ACT 128358277730 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 514715040 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 280846500 # Energy for precharge commands per rank (pJ)
+system.physmem_1.actEnergy 514722600 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 280850625 # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy 1226721600 # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy 212706000 # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy 26739067680 # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy 96210213075 # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy 161236503750 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 286420773645 # Total energy per rank (pJ)
-system.physmem_1.averagePower 699.635490 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 267598080337 # Time in different power states
+system.physmem_1.totalEnergy 286420785330 # Total energy per rank (pJ)
+system.physmem_1.averagePower 699.635519 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 267597865087 # Time in different power states
system.physmem_1.memoryStateTime::REF 13670280000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem_1.memoryStateTime::ACT 128117581163 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.cpu.branchPred.lookups 233960254 # Number of BP lookups
-system.cpu.branchPred.condPredicted 161822373 # Number of conditional branches predicted
+system.cpu.branchPred.lookups 233960267 # Number of BP lookups
+system.cpu.branchPred.condPredicted 161822378 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15514618 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 121575796 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 108259792 # Number of BTB hits
+system.cpu.branchPred.BTBLookups 121575807 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 108259798 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 89.047159 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 89.047156 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 25036830 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1300193 # Number of incorrect RAS predictions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.itb.misses 0 # DTB misses
system.cpu.itb.accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 673 # Number of system calls
-system.cpu.numCycles 818776683 # number of cpu cycles simulated
+system.cpu.numCycles 818776833 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 84080283 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 1200690611 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 233960254 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 133296622 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 718833631 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.icacheStallCycles 84080281 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 1200690651 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 233960267 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 133296628 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 718834157 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 31063665 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 2156 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.MiscStallCycles 2157 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 31 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 3279 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 370702181 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 652815 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 818451212 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.833527 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.IcacheWaitRetryStallCycles 3294 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 370702196 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 652814 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.rateDist::samples 818451752 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 1.833525 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.163546 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 136785734 16.71% 16.71% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 223134622 27.26% 43.98% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 98075130 11.98% 55.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 360455726 44.04% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 136786252 16.71% 16.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 223134631 27.26% 43.98% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 98075133 11.98% 55.96% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 360455736 44.04% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 818451212 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::total 818451752 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.285744 # Number of branch fetches per cycle
-system.cpu.fetch.rate 1.466445 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 119992571 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 159648210 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 484662538 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 38629741 # Number of cycles decode is unblocking
+system.cpu.fetch.rate 1.466444 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 119992574 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 159648734 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 484662553 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 38629739 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 15518152 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 25181026 # Number of times decode resolved a branch
+system.cpu.decode.BranchResolved 25181029 # Number of times decode resolved a branch
system.cpu.decode.BranchMispred 13828 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 1248127712 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 39967189 # Number of squashed instructions handled by decode
+system.cpu.decode.DecodedInsts 1248127732 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 39967182 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 15518152 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 177000170 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 78888622 # Number of cycles rename is blocking
+system.cpu.rename.IdleCycles 177000175 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 78889127 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 210704 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 464955823 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 81877741 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 1190635480 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 25549977 # Number of squashed instructions processed by rename
+system.cpu.rename.RunCycles 464955834 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 81877760 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 1190635501 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 25549976 # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents 24948594 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 2267380 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 41534187 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 1694220 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 1225376851 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 5812387634 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1358166964 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 1694237 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 1225376861 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 5812387733 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1358166990 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 40876517 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 874778230 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 350598621 # Number of HB maps that are undone due to squashing
+system.cpu.rename.UndoneMaps 350598631 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 7265 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 7257 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 108139964 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 366113107 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 236095924 # Number of stores inserted to the mem dependence unit.
+system.cpu.rename.skidInsts 108139973 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 366113111 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 236095933 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 1592417 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 5322589 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 1168545112 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsAdded 1168545131 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 12357 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 1017136895 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 18518107 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 379832511 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 1032101117 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 1017136914 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 18518110 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 379832530 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 1032101126 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 203 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 818451212 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.242758 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 818451752 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 1.242757 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.084999 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 260801504 31.87% 31.87% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 227738074 27.83% 59.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 216482418 26.45% 86.14% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 97282888 11.89% 98.03% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 16146319 1.97% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 260802028 31.87% 31.87% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 227738086 27.83% 59.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 216482422 26.45% 86.14% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 97282889 11.89% 98.03% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 16146318 1.97% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 818451212 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 818451752 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 64511713 19.12% 19.12% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 18146 0.01% 19.13% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 19.32% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 19.32% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 155540663 46.10% 65.42% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 116678902 34.58% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 155540667 46.10% 65.42% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 116678907 34.58% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 456370981 44.87% 44.87% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 456370990 44.87% 44.87% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 5195830 0.51% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 45.38% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.13% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.13% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 322128329 31.67% 78.80% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 215587412 21.20% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 322128333 31.67% 78.80% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 215587418 21.20% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 1017136895 # Type of FU issued
+system.cpu.iq.FU_type_0::total 1017136914 # Type of FU issued
system.cpu.iq.rate 1.242264 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 337386313 # FU busy when requested
+system.cpu.iq.fu_busy_cnt 337386322 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.331702 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 3146752380 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 1504842501 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 934271178 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.int_inst_queue_reads 3146752970 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 1504842539 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 934271199 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 61877042 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 43565869 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 26152443 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 1320712858 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 1320712886 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 33810350 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 9960171 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 113872169 # Number of loads squashed
+system.cpu.iew.lsq.thread0.squashedLoads 113872173 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 1090 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 18393 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 107115428 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedStores 107115437 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2065797 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 22350 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 15518152 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 35325435 # Number of cycles IEW is blocking
+system.cpu.iew.iewBlockCycles 35325436 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 42128 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 1168563023 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispatchedInsts 1168563042 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 366113107 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 236095924 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 366113111 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 236095933 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6617 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 102 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 45749 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.predictedTakenIncorrect 15437385 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3784510 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 19221895 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 974751162 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 303297617 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 42385733 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 974751184 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 303297622 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 42385730 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 5554 # number of nop insts executed
-system.cpu.iew.exec_refs 497765227 # number of memory reference insts executed
-system.cpu.iew.exec_branches 150613464 # Number of branches executed
-system.cpu.iew.exec_stores 194467610 # Number of stores executed
+system.cpu.iew.exec_refs 497765238 # number of memory reference insts executed
+system.cpu.iew.exec_branches 150613469 # Number of branches executed
+system.cpu.iew.exec_stores 194467616 # Number of stores executed
system.cpu.iew.exec_rate 1.190497 # Inst execution rate
-system.cpu.iew.wb_sent 963723916 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 960423621 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 536680580 # num instructions producing a value
-system.cpu.iew.wb_consumers 893282190 # num instructions consuming a value
+system.cpu.iew.wb_sent 963723937 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 960423642 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 536680583 # num instructions producing a value
+system.cpu.iew.wb_consumers 893282195 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.172998 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.600796 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 357407190 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 357407209 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 12154 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 15500938 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 767630958 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 1.027486 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.786865 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::samples 767631497 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::mean 1.027485 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.786864 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 430922921 56.14% 56.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 172477665 22.47% 78.61% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 430923455 56.14% 56.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 172477669 22.47% 78.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 73566542 9.58% 88.19% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 31624091 4.12% 92.31% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 31624094 4.12% 92.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 8540357 1.11% 93.42% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 14250533 1.86% 95.28% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 14250532 1.86% 95.28% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 7269334 0.95% 96.22% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 6619169 0.86% 97.09% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 22360346 2.91% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 22360345 2.91% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.committedOps 788730070 # Number of ops (including micro ops) committed
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system.cpu.committedInsts 640649299 # Number of Instructions Simulated
system.cpu.committedOps 788724958 # Number of Ops (including micro ops) Simulated
system.cpu.cpi 1.278042 # CPI: Cycles Per Instruction
system.cpu.cpi_total 1.278042 # CPI: Total CPI of All Threads
system.cpu.ipc 0.782447 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.782447 # IPC: Total IPC of All Threads
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system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71806.752624 # average ReadExReq miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.overall_mshr_hits::cpu.inst 14 # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data 2747 # number of overall MSHR hits
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system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 17078829649 # number of HardPFReq MSHR miss cycles
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-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.053222 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015527 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
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-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.001939 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.001939 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000684 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.000685 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.014291 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.039812 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.039804 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 65009.052275 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70230.092661 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70064.956395 # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70231.885429 # average ReadReq mshr miss latency
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system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 84447.491861 # average HardPFReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13778.777778 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 13778.777778 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 13790.473684 # average UpgradeReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81552.580830 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 81552.580830 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65009.052275 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70374.318979 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 84447.491861 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.449525 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79334.229787 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 7206353 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 7206352 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 7206354 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 7206353 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 735673 # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq 248887 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 19 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 19 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 720846 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 720846 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 10340987 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6249103 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 16590090 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 330910976 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 16590092 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 223511616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 554422592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 554422656 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 248905 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 8911778 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.027928 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 8911779 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.027928 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.164766 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 8662891 97.21% 97.21% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 248887 2.79% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 8662892 97.21% 97.21% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 248887 2.79% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 8911778 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 5067118500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 8911779 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 5067119000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 7756291499 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 7756292749 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 4138722865 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 4138723116 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.membus.trans_dist::ReadReq 314057 # Transaction distribution
-system.membus.trans_dist::ReadResp 314057 # Transaction distribution
+system.membus.trans_dist::ReadReq 314058 # Transaction distribution
+system.membus.trans_dist::ReadResp 314058 # Transaction distribution
system.membus.trans_dist::Writeback 66342 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 18 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 18 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 19 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 19 # Transaction distribution
system.membus.trans_dist::ReadExReq 1398 # Transaction distribution
system.membus.trans_dist::ReadExResp 1398 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 697288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435008 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 24435008 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 697292 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 697292 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 24435072 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 24435072 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 381815 # Request fanout histogram
+system.membus.snoop_fanout::samples 381817 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 381815 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 381817 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 381815 # Request fanout histogram
-system.membus.reqLayer0.occupancy 746604866 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 381817 # Request fanout histogram
+system.membus.reqLayer0.occupancy 746606366 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.membus.respLayer1.occupancy 1648190996 # Layer occupancy (ticks)
+system.membus.respLayer1.occupancy 1648197495 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 395726778500 # Number of ticks simulated
final_tick 395726778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1109777 # Simulator instruction rate (inst/s)
-host_op_rate 1366282 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 685499869 # Simulator tick rate (ticks/s)
-host_mem_usage 303676 # Number of bytes of host memory used
-host_seconds 577.28 # Real time elapsed on the host
+host_inst_rate 1575908 # Simulator instruction rate (inst/s)
+host_op_rate 1940150 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 973424664 # Simulator tick rate (ticks/s)
+host_mem_usage 311080 # Number of bytes of host memory used
+host_seconds 406.53 # Real time elapsed on the host
sim_insts 640654411 # Number of instructions simulated
sim_ops 788730070 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 4241547525 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 1022670353 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.629116 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.629116 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.483042 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 379292454 37.09% 37.09% # Request fanout histogram
-system.membus.snoop_fanout::3 643377899 62.91% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 379292454 37.09% 37.09% # Request fanout histogram
+system.membus.snoop_fanout::1 643377899 62.91% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 1022670353 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 56570304 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 883911 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 883911 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 883911 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 883911 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 533516500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
sim_ticks 57716694500 # Number of ticks simulated
final_tick 57716694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 141604 # Simulator instruction rate (inst/s)
-host_op_rate 181090 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 115249030 # Simulator tick rate (ticks/s)
-host_mem_usage 314220 # Number of bytes of host memory used
-host_seconds 500.80 # Real time elapsed on the host
+host_inst_rate 194770 # Simulator instruction rate (inst/s)
+host_op_rate 249082 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 158520150 # Simulator tick rate (ticks/s)
+host_mem_usage 322420 # Number of bytes of host memory used
+host_seconds 364.10 # Real time elapsed on the host
sim_insts 70915128 # Number of instructions simulated
sim_ops 90690084 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 21367424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 333867 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 333867 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 333867 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 333867 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 295378500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
sim_ticks 33330913000 # Number of ticks simulated
final_tick 33330913000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 93420 # Simulator instruction rate (inst/s)
-host_op_rate 119473 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 43913176 # Simulator tick rate (ticks/s)
-host_mem_usage 317168 # Number of bytes of host memory used
-host_seconds 759.02 # Real time elapsed on the host
+host_inst_rate 123947 # Simulator instruction rate (inst/s)
+host_op_rate 158514 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58262578 # Simulator tick rate (ticks/s)
+host_mem_usage 323704 # Number of bytes of host memory used
+host_seconds 572.08 # Real time elapsed on the host
sim_insts 70907630 # Number of instructions simulated
sim_ops 90682585 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 68691776 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 151304 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1224624 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.123542 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.123542 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.329058 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 1073332 87.65% 87.65% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 151292 12.35% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1073332 87.65% 87.65% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 151292 12.35% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1224624 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 801075000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.4 # Layer utilization (%)
sim_ticks 1121265462500 # Number of ticks simulated
final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175724 # Simulator instruction rate (inst/s)
-host_op_rate 189316 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 127565822 # Simulator tick rate (ticks/s)
-host_mem_usage 306448 # Number of bytes of host memory used
-host_seconds 8789.70 # Real time elapsed on the host
+host_inst_rate 238084 # Simulator instruction rate (inst/s)
+host_op_rate 256500 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 172835636 # Simulator tick rate (ticks/s)
+host_mem_usage 314372 # Number of bytes of host memory used
+host_seconds 6487.47 # Real time elapsed on the host
sim_insts 1544563088 # Number of instructions simulated
sim_ops 1664032481 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 12928956 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
sim_ticks 771725169000 # Number of ticks simulated
final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 109963 # Simulator instruction rate (inst/s)
-host_op_rate 118469 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 54942138 # Simulator tick rate (ticks/s)
-host_mem_usage 305172 # Number of bytes of host memory used
-host_seconds 14046.14 # Real time elapsed on the host
+host_inst_rate 137392 # Simulator instruction rate (inst/s)
+host_op_rate 148019 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68646343 # Simulator tick rate (ticks/s)
+host_mem_usage 311812 # Number of bytes of host memory used
+host_seconds 11242.04 # Real time elapsed on the host
sim_insts 1544563024 # Number of instructions simulated
sim_ops 1664032416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 1298291 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
sim_ticks 832017490500 # Number of ticks simulated
final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1379227 # Simulator instruction rate (inst/s)
-host_op_rate 1485908 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 742955189 # Simulator tick rate (ticks/s)
-host_mem_usage 295688 # Number of bytes of host memory used
-host_seconds 1119.88 # Real time elapsed on the host
+host_inst_rate 1936914 # Simulator instruction rate (inst/s)
+host_op_rate 2086731 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1043366913 # Simulator tick rate (ticks/s)
+host_mem_usage 303348 # Number of bytes of host memory used
+host_seconds 797.44 # Real time elapsed on the host
sim_insts 1544563042 # Number of instructions simulated
sim_ops 1664032434 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 8383808423 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 2172060895 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.711106 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.711106 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 627495305 28.89% 28.89% # Request fanout histogram
-system.membus.snoop_fanout::3 1544565590 71.11% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 627495305 28.89% 28.89% # Request fanout histogram
+system.membus.snoop_fanout::1 1544565590 71.11% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 2172060895 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 12813292 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 12813292 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%)
sim_ticks 2846007227500 # Number of ticks simulated
final_tick 2846007227500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1299561 # Simulator instruction rate (inst/s)
-host_op_rate 2024834 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1229541445 # Simulator tick rate (ticks/s)
-host_mem_usage 299440 # Number of bytes of host memory used
-host_seconds 2314.69 # Real time elapsed on the host
+host_inst_rate 1464727 # Simulator instruction rate (inst/s)
+host_op_rate 2282177 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1385807923 # Simulator tick rate (ticks/s)
+host_mem_usage 304512 # Number of bytes of host memory used
+host_seconds 2053.68 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 11281019509 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2307979078 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13588998587 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
-system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
-system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
-system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.705196 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1677713084 29.48% 29.48% # Request fanout histogram
-system.membus.snoop_fanout::3 4013232882 70.52% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 46 # Number of system calls
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 4686862596 # Class of executed instruction
+system.membus.trans_dist::ReadReq 5252417628 # Transaction distribution
+system.membus.trans_dist::ReadResp 5252417628 # Transaction distribution
+system.membus.trans_dist::WriteReq 438528338 # Transaction distribution
+system.membus.trans_dist::WriteResp 438528338 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 8026465764 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 8026465764 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3355426168 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 3355426168 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 11381891932 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 32105863056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 32105863056 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 6568525137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 6568525137 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 38674388193 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 5690945966 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.705196 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.455955 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1677713084 29.48% 29.48% # Request fanout histogram
+system.membus.snoop_fanout::1 4013232882 70.52% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 5690945966 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 5882580398500 # Number of ticks simulated
final_tick 5882580398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 733187 # Simulator instruction rate (inst/s)
-host_op_rate 1142372 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1433815394 # Simulator tick rate (ticks/s)
-host_mem_usage 313792 # Number of bytes of host memory used
-host_seconds 4102.75 # Real time elapsed on the host
+host_inst_rate 739516 # Simulator instruction rate (inst/s)
+host_op_rate 1152234 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1446192754 # Simulator tick rate (ticks/s)
+host_mem_usage 314252 # Number of bytes of host memory used
+host_seconds 4067.63 # Real time elapsed on the host
sim_insts 3008081022 # Number of instructions simulated
sim_ops 4686862596 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 819923712 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 12811308 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 12811308 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 12811308 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 12811308 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 10103610000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
sim_ticks 131767151500 # Number of ticks simulated
final_tick 131767151500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 176753 # Simulator instruction rate (inst/s)
-host_op_rate 186327 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 135158895 # Simulator tick rate (ticks/s)
-host_mem_usage 309748 # Number of bytes of host memory used
-host_seconds 974.91 # Real time elapsed on the host
+host_inst_rate 244794 # Simulator instruction rate (inst/s)
+host_op_rate 258052 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 187187675 # Simulator tick rate (ticks/s)
+host_mem_usage 317932 # Number of bytes of host memory used
+host_seconds 703.93 # Real time elapsed on the host
sim_insts 172317810 # Number of instructions simulated
sim_ops 181650743 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 417024 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6517 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 6517 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 6517 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6517 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3274500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
sim_ticks 85032044000 # Number of ticks simulated
final_tick 85032044000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 98638 # Simulator instruction rate (inst/s)
-host_op_rate 103981 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 48678127 # Simulator tick rate (ticks/s)
-host_mem_usage 307440 # Number of bytes of host memory used
-host_seconds 1746.82 # Real time elapsed on the host
+host_inst_rate 135904 # Simulator instruction rate (inst/s)
+host_op_rate 143266 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 67069129 # Simulator tick rate (ticks/s)
+host_mem_usage 314096 # Number of bytes of host memory used
+host_seconds 1267.83 # Real time elapsed on the host
sim_insts 172303022 # Number of instructions simulated
sim_ops 181635954 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 12368832 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 2153 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 195416 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011018 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.011018 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.104385 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 193263 98.90% 98.90% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 2153 1.10% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 193263 98.90% 98.90% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 2153 1.10% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 195416 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 161509500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
sim_ticks 81224844500 # Number of ticks simulated
final_tick 81224844500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 72712 # Simulator instruction rate (inst/s)
-host_op_rate 121872 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 44718419 # Simulator tick rate (ticks/s)
-host_mem_usage 340792 # Number of bytes of host memory used
-host_seconds 1816.36 # Real time elapsed on the host
+host_inst_rate 91947 # Simulator instruction rate (inst/s)
+host_op_rate 154111 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56548085 # Simulator tick rate (ticks/s)
+host_mem_usage 347388 # Number of bytes of host memory used
+host_seconds 1436.39 # Real time elapsed on the host
sim_insts 132071192 # Number of instructions simulated
sim_ops 221363384 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 631040 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 299 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 10459 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 10459 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 10459 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 10459 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 5242500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
sim_ticks 1869358498000 # Number of ticks simulated
final_tick 1869358498000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1825215 # Simulator instruction rate (inst/s)
-host_op_rate 1825215 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 52491614317 # Simulator tick rate (ticks/s)
-host_mem_usage 318168 # Number of bytes of host memory used
-host_seconds 35.61 # Real time elapsed on the host
+host_inst_rate 2576820 # Simulator instruction rate (inst/s)
+host_op_rate 2576818 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 74107088123 # Simulator tick rate (ticks/s)
+host_mem_usage 319644 # Number of bytes of host memory used
+host_seconds 25.23 # Real time elapsed on the host
sim_insts 65000470 # Number of instructions simulated
sim_ops 65000470 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size_system.iocache.mem_side::total 5328064 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 78784210 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 1265678 # Request fanout histogram
+system.membus.snoop_fanout::samples 1287715 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 1265678 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 1287715 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 1265678 # Request fanout histogram
+system.membus.snoop_fanout::total 1287715 # Request fanout histogram
system.toL2Bus.trans_dist::ReadReq 2732182 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 2732182 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 14588 # Transaction distribution
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 23357975 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 243126610 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 41895 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3873082 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.010775 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.103240 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3895119 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 3.010714 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.102951 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3831351 98.92% 98.92% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 41731 1.08% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 3853388 98.93% 98.93% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 41731 1.07% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3873082 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3895119 # Request fanout histogram
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
sim_ticks 1829332273500 # Number of ticks simulated
final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1690642 # Simulator instruction rate (inst/s)
-host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51512796649 # Simulator tick rate (ticks/s)
-host_mem_usage 313048 # Number of bytes of host memory used
-host_seconds 35.51 # Real time elapsed on the host
+host_inst_rate 2059947 # Simulator instruction rate (inst/s)
+host_op_rate 2059945 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 62765242809 # Simulator tick rate (ticks/s)
+host_mem_usage 317596 # Number of bytes of host memory used
+host_seconds 29.15 # Real time elapsed on the host
sim_insts 60038341 # Number of instructions simulated
sim_ops 60038341 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 41883 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3855738 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.010822 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.103463 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3814012 98.92% 98.92% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 41726 1.08% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3855738 # Request fanout histogram
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 1215692 # Request fanout histogram
+system.membus.snoop_fanout::samples 1232714 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 1232714 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 1215692 # Request fanout histogram
+system.membus.snoop_fanout::total 1232714 # Request fanout histogram
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
sim_ticks 1962612686500 # Number of ticks simulated
final_tick 1962612686500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1051716 # Simulator instruction rate (inst/s)
-host_op_rate 1051715 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 33894179183 # Simulator tick rate (ticks/s)
-host_mem_usage 374244 # Number of bytes of host memory used
-host_seconds 57.90 # Real time elapsed on the host
+host_inst_rate 1118839 # Simulator instruction rate (inst/s)
+host_op_rate 1118839 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 36057415911 # Simulator tick rate (ticks/s)
+host_mem_usage 319640 # Number of bytes of host memory used
+host_seconds 54.43 # Real time elapsed on the host
sim_insts 60898638 # Number of instructions simulated
sim_ops 60898638 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.demand_mshr_misses::total 1190299 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data 1190299 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 1190299 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 7110 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 7110 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 10834 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 10834 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 17944 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 17944 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 27526583001 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 27526583001 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 10476952065 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31927.721578 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 31927.721578 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 207372.151899 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 207372.151899 # average ReadReq mshr uncacheable latency
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+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 211730.893483 # average WriteReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 210003.817432 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 698758 # number of replacements
system.cpu0.icache.tags.tagsinuse 508.155937 # Cycle average of tags in use
system.cpu1.dcache.demand_mshr_misses::total 180698 # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data 180698 # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total 180698 # number of overall MSHR misses
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system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1250643250 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1250643250 # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1167915001 # number of WriteReq MSHR miss cycles
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 13384.532485 # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 13384.532485 # average overall mshr miss latency
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-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 222327.184760 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 315648 # number of replacements
system.cpu1.icache.tags.tagsinuse 445.931523 # Cycle average of tags in use
system.l2c.overall_mshr_misses::cpu1.inst 449 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 6823 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 407602 # number of overall MSHR misses
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system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 888765750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 16305067500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 31138500 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 69350.779510 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69366.189946 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 61445.734449 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 292759 # Transaction distribution
system.membus.trans_dist::ReadResp 292759 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 5317568 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 36482026 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 21558 # Total snoops (count)
-system.membus.snoop_fanout::samples 597341 # Request fanout histogram
+system.membus.snoop_fanout::samples 618592 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 597341 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 597341 # Request fanout histogram
+system.membus.snoop_fanout::total 618592 # Request fanout histogram
system.membus.reqLayer0.occupancy 40208000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1232118814 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 17747522 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 201680554 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 98552 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3255455 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.012829 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.112536 # Request fanout histogram
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system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3213691 98.72% 98.72% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 41764 1.28% 100.00% # Request fanout histogram
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system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3255455 # Request fanout histogram
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system.toL2Bus.reqLayer0.occupancy 2417745499 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 238500 # Layer occupancy (ticks)
sim_ticks 1922413663500 # Number of ticks simulated
final_tick 1922413663500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1122927 # Simulator instruction rate (inst/s)
-host_op_rate 1122927 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 38428929684 # Simulator tick rate (ticks/s)
-host_mem_usage 370248 # Number of bytes of host memory used
-host_seconds 50.03 # Real time elapsed on the host
+host_inst_rate 912210 # Simulator instruction rate (inst/s)
+host_op_rate 912209 # Simulator op (including micro ops) rate (op/s)
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+host_mem_usage 318584 # Number of bytes of host memory used
+host_seconds 61.58 # Real time elapsed on the host
sim_insts 56174594 # Number of instructions simulated
sim_ops 56174594 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 1374617 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 1374617 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 1374617 # number of overall MSHR misses
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system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 29166094500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 29166094500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11190140370 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29358.166580 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 29358.166580 # average overall mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 208576.839566 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 928205 # number of replacements
system.cpu.icache.tags.tagsinuse 508.070911 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 13291 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 388821 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 402112 # number of overall MSHR misses
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+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 16580 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 897481500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 16318511000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 17215992500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67525.505981 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61143.505929 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61354.450051 # average overall mshr miss latency
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-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 195158.866104 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2023514 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2023497 # Transaction distribution
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 142615892 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 202062676 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 41937 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3198175 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 1.013058 # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 3156414 98.69% 98.69% # Request fanout histogram
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system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3198175 # Request fanout histogram
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system.cpu.toL2Bus.reqLayer0.occupancy 2426956000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 234000 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 5317056 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 35819412 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 431 # Total snoops (count)
-system.membus.snoop_fanout::samples 559589 # Request fanout histogram
+system.membus.snoop_fanout::samples 576169 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 559589 100.00% 100.00% # Request fanout histogram
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system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 559589 # Request fanout histogram
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system.membus.reqLayer0.occupancy 30034000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 1195840311 # Layer occupancy (ticks)
sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 903946 # Simulator instruction rate (inst/s)
-host_op_rate 1100409 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17625645989 # Simulator tick rate (ticks/s)
-host_mem_usage 615176 # Number of bytes of host memory used
-host_seconds 157.94 # Real time elapsed on the host
+host_inst_rate 1057273 # Simulator instruction rate (inst/s)
+host_op_rate 1287060 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20615299474 # Simulator tick rate (ticks/s)
+host_mem_usage 562992 # Number of bytes of host memory used
+host_seconds 135.04 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 359045 # Request fanout histogram
+system.membus.snoop_fanout::samples 426678 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 359045 # Request fanout histogram
+system.membus.snoop_fanout::total 426678 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
sim_ticks 2802894699500 # Number of ticks simulated
final_tick 2802894699500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1337323 # Simulator instruction rate (inst/s)
-host_op_rate 1629508 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25528979782 # Simulator tick rate (ticks/s)
-host_mem_usage 626168 # Number of bytes of host memory used
-host_seconds 109.79 # Real time elapsed on the host
+host_inst_rate 935329 # Simulator instruction rate (inst/s)
+host_op_rate 1139685 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17855077822 # Simulator tick rate (ticks/s)
+host_mem_usage 572752 # Number of bytes of host memory used
+host_seconds 156.98 # Real time elapsed on the host
sim_insts 146828240 # Number of instructions simulated
sim_ops 178908039 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1117604 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 9440956 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 152020 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1081568 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1118628 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 9439908 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 149524 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1084244 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11793812 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1117604 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 152020 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1269624 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8390656 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11793968 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1118628 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 149524 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1268152 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8394176 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8408400 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8411740 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 25916 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 148040 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2530 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16923 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 25932 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 148018 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2491 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 16962 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 193435 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 131104 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 193429 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 131159 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 135540 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 135550 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 183 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 398732 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3368288 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 54237 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 385875 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 399097 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3367914 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 53346 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 386830 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4207726 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 398732 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 54237 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 452969 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2993568 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4207781 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 399097 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 53346 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 452444 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2994824 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6252 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2999899 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2993568 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 3001090 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2994824 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 183 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 398732 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3374604 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 54237 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 385890 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 399097 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3374166 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 53346 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 386844 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 343 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7207624 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7208872 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.cpu0.op_class::total 116882065 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1968 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 693477 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 494.853657 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 35932369 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 693989 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 51.776569 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853657 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.replacements 693486 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 494.853665 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 35932410 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 693998 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 51.775956 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853665 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 74113775 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 74113775 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 19108539 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 19108539 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 15690376 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 15690376 # number of WriteReq hits
+system.cpu0.dcache.tags.tag_accesses 74113887 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 74113887 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 19108541 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 19108541 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 15690414 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 15690414 # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346093 # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total 346093 # number of SoftPFReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379629 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 379629 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363049 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 363049 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 34798915 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 34798915 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 35145008 # number of overall hits
-system.cpu0.dcache.overall_hits::total 35145008 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 373099 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 373099 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 295764 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 295764 # number of WriteReq misses
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+system.cpu0.dcache.StoreCondReq_hits::total 363041 # number of StoreCondReq hits
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+system.cpu0.dcache.overall_hits::total 35145048 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 373103 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 295771 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 295771 # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100321 # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total 100321 # number of SoftPFReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6742 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 6742 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18436 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 18436 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 668863 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 668863 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 769184 # number of overall misses
-system.cpu0.dcache.overall_misses::total 769184 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481638 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 19481638 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986140 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 15986140 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 668874 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 668874 # number of demand (read+write) misses
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+system.cpu0.dcache.overall_misses::total 769195 # number of overall misses
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+system.cpu0.dcache.WriteReq_accesses::total 15986185 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446414 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total 446414 # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386371 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 386371 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381485 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 381485 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 35467778 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 35467778 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses
+system.cpu0.dcache.demand_accesses::cpu0.data 35467829 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 35467829 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 35914243 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 35914243 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019152 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.019152 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018502 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.018502 # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224726 # miss rate for SoftPFReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017450 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017450 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048327 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048327 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses
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system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks 192974 # number of writebacks
-system.cpu0.l2cache.writebacks::total 192974 # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks 193152 # number of writebacks
+system.cpu0.l2cache.writebacks::total 193152 # number of writebacks
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1651840 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1651840 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28386 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28386 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 511896 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 26247 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18436 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 44683 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 269517 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 269517 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq 1651838 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1651838 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28341 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28341 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 511485 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 26248 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 44692 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 269523 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 269523 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238556 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220556 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220081 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28808 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4500748 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4500273 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71092472 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80931536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80905668 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57616 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 152107280 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 322019 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 2656743 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.082586 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.275256 # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total 152081412 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 327909 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 2731172 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.090112 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.286342 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 2437332 91.74% 91.74% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 219411 8.26% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 2485061 90.99% 90.99% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 246111 9.01% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2656743 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 2731172 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.dcache.tags.data_accesses 39751979 # Number of data accesses
system.cpu1.dcache.ReadReq_hits::cpu1.data 11858694 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 11858694 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 7397494 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 7397494 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 7397479 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 7397479 # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50099 # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total 50099 # number of SoftPFReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 91447 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 91447 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 72460 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 72460 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 19256188 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 19256188 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 19306287 # number of overall hits
-system.cpu1.dcache.overall_hits::total 19306287 # number of overall hits
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+system.cpu1.dcache.StoreCondReq_hits::total 72442 # number of StoreCondReq hits
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+system.cpu1.dcache.demand_hits::total 19256173 # number of demand (read+write) hits
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+system.cpu1.dcache.overall_hits::total 19306272 # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data 136630 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 136630 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 92468 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 92468 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 92483 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 92483 # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30719 # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total 30719 # number of SoftPFReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5318 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 5318 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22519 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 22519 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 229098 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 229098 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 259817 # number of overall misses
-system.cpu1.dcache.overall_misses::total 259817 # number of overall misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 22537 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 22537 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 229113 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 229113 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 259832 # number of overall misses
+system.cpu1.dcache.overall_misses::total 259832 # number of overall misses
system.cpu1.dcache.ReadReq_accesses::cpu1.data 11995324 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 11995324 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data 7489962 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.overall_accesses::total 19566104 # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.011390 # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total 0.011390 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012346 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.012346 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.012348 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.012348 # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.380101 # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380101 # miss rate for SoftPFReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.054958 # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237095 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237095 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011757 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.011757 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013279 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.013279 # miss rate for overall accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.237284 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237284 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.011758 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.011758 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.013280 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.013280 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 120855 # number of writebacks
-system.cpu1.dcache.writebacks::total 120855 # number of writebacks
+system.cpu1.dcache.writebacks::writebacks 120843 # number of writebacks
+system.cpu1.dcache.writebacks::total 120843 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.icache.tags.replacements 523373 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.711129 # Cycle average of tags in use
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 48604 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 15305.333897 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 716708 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 63433 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 11.298662 # Average number of references to valid blocks.
+system.cpu1.l2cache.tags.replacements 48543 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 15314.912528 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 717091 # Total number of references to valid blocks.
+system.cpu1.l2cache.tags.sampled_refs 63380 # Sample count of references to valid blocks.
+system.cpu1.l2cache.tags.avg_refs 11.314153 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l2cache.tags.occ_blocks::writebacks 8327.809694 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 4.091002 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.023143 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3278.979607 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3692.430451 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_percent::writebacks 0.508289 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000250 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000123 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.200133 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.225368 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_percent::total 0.934163 # Average percentage of cache occupancy
-system.cpu1.l2cache.tags.occ_task_id_blocks::1023 22 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14807 # Occupied blocks per task id
+system.cpu1.l2cache.tags.occ_blocks::writebacks 8302.426392 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 3.123905 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.034953 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3306.071742 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3701.255535 # Average occupied blocks per requestor
+system.cpu1.l2cache.tags.occ_percent::writebacks 0.506740 # Average percentage of cache occupancy
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+system.cpu1.l2cache.tags.occ_percent::total 0.934748 # Average percentage of cache occupancy
+system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id
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system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 539 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9357 # Occupied blocks per task id
-system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4911 # Occupied blocks per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001343 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903748 # Percentage of cache occupancy per task id
-system.cpu1.l2cache.tags.tag_accesses 15213345 # Number of tag accesses
-system.cpu1.l2cache.tags.data_accesses 15213345 # Number of data accesses
-system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3151 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 1735 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.inst 510036 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::cpu1.data 99375 # number of ReadReq hits
-system.cpu1.l2cache.ReadReq_hits::total 614297 # number of ReadReq hits
-system.cpu1.l2cache.Writeback_hits::writebacks 120855 # number of Writeback hits
-system.cpu1.l2cache.Writeback_hits::total 120855 # number of Writeback hits
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 9377 # Occupied blocks per task id
+system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4900 # Occupied blocks per task id
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+system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.903809 # Percentage of cache occupancy per task id
+system.cpu1.l2cache.tags.tag_accesses 15213000 # Number of tag accesses
+system.cpu1.l2cache.tags.data_accesses 15213000 # Number of data accesses
+system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 3125 # number of ReadReq hits
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+system.cpu1.l2cache.ReadReq_hits::cpu1.data 99394 # number of ReadReq hits
+system.cpu1.l2cache.ReadReq_hits::total 614287 # number of ReadReq hits
+system.cpu1.l2cache.Writeback_hits::writebacks 120843 # number of Writeback hits
+system.cpu1.l2cache.Writeback_hits::total 120843 # number of Writeback hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 8 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 8 # number of UpgradeReq hits
-system.cpu1.l2cache.ReadExReq_hits::cpu1.data 19784 # number of ReadExReq hits
-system.cpu1.l2cache.ReadExReq_hits::total 19784 # number of ReadExReq hits
-system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 3151 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.itb.walker 1735 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.inst 510036 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::cpu1.data 119159 # number of demand (read+write) hits
-system.cpu1.l2cache.demand_hits::total 634081 # number of demand (read+write) hits
-system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 3151 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.itb.walker 1735 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.inst 510036 # number of overall hits
-system.cpu1.l2cache.overall_hits::cpu1.data 119159 # number of overall hits
-system.cpu1.l2cache.overall_hits::total 634081 # number of overall hits
-system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 338 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 261 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.inst 13849 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::cpu1.data 73292 # number of ReadReq misses
-system.cpu1.l2cache.ReadReq_misses::total 87740 # number of ReadReq misses
-system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28844 # number of UpgradeReq misses
-system.cpu1.l2cache.UpgradeReq_misses::total 28844 # number of UpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22519 # number of SCUpgradeReq misses
-system.cpu1.l2cache.SCUpgradeReq_misses::total 22519 # number of SCUpgradeReq misses
-system.cpu1.l2cache.ReadExReq_misses::cpu1.data 43832 # number of ReadExReq misses
-system.cpu1.l2cache.ReadExReq_misses::total 43832 # number of ReadExReq misses
-system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 338 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.itb.walker 261 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.inst 13849 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::cpu1.data 117124 # number of demand (read+write) misses
-system.cpu1.l2cache.demand_misses::total 131572 # number of demand (read+write) misses
-system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 338 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.itb.walker 261 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.inst 13849 # number of overall misses
-system.cpu1.l2cache.overall_misses::cpu1.data 117124 # number of overall misses
-system.cpu1.l2cache.overall_misses::total 131572 # number of overall misses
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-system.cpu1.l2cache.Writeback_accesses::total 120855 # number of Writeback accesses(hits+misses)
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system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 63616 # number of ReadExReq accesses(hits+misses)
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system.cpu1.l2cache.overall_accesses::cpu1.data 236283 # number of overall (read+write) accesses
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system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999723 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
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-system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.495694 # miss rate for overall accesses
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+system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.495499 # miss rate for demand accesses
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system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 709301 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709301 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 120855 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 28852 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22519 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 51371 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 120843 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 28867 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22537 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 51404 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 63616 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 63616 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048124 # Packet count per connected master and slave (bytes)
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system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12078 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 1774441 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 1774495 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33529348 # Cumulative packet size per connected master and slave (bytes)
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system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24156 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 56442750 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 499492 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1371571 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.313385 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.463870 # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total 56441982 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 568922 # Total snoops (count)
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+system.cpu1.toL2Bus.snoop_fanout::mean 1.351508 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.477442 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 941741 68.66% 68.66% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 429830 31.34% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 938322 64.85% 64.85% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 508608 35.15% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1371571 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1446930 # Request fanout histogram
system.iobus.trans_dist::ReadReq 30995 # Transaction distribution
system.iobus.trans_dist::ReadResp 30995 # Transaction distribution
system.iobus.trans_dist::WriteReq 59419 # Transaction distribution
system.iocache.writebacks::writebacks 36190 # number of writebacks
system.iocache.writebacks::total 36190 # number of writebacks
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 107683 # number of replacements
-system.l2c.tags.tagsinuse 62052.473518 # Cycle average of tags in use
-system.l2c.tags.total_refs 207875 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 168125 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 1.236431 # Average number of references to valid blocks.
+system.l2c.tags.replacements 107655 # number of replacements
+system.l2c.tags.tagsinuse 62149.484460 # Cycle average of tags in use
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+system.l2c.tags.avg_refs 1.240569 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 48595.677496 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972785 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030393 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 7329.722723 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3756.747244 # Average occupied blocks per requestor
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-system.l2c.tags.occ_blocks::cpu1.inst 1654.505866 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 710.993782 # Average occupied blocks per requestor
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system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.inst 0.025246 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.010849 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.946846 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 7 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 60435 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 68 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1875 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 13095 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 45357 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000107 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.922165 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 4904261 # Number of tag accesses
-system.l2c.tags.data_accesses 4904261 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 71 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 27858 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 76068 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 39 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 20 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 11484 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 11410 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 127013 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 225951 # number of Writeback hits
-system.l2c.Writeback_hits::total 225951 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 487 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 552 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 64 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 10 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 74 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 13938 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 3112 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 17050 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 71 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 27858 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 90006 # number of demand (read+write) hits
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+system.l2c.demand_miss_rate::cpu1.data 0.540772 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.560512 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.091954 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.025000 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.375983 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.621223 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.023256 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.168246 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.540772 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.560512 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 94914 # number of writebacks
-system.l2c.writebacks::total 94914 # number of writebacks
+system.l2c.writebacks::writebacks 94969 # number of writebacks
+system.l2c.writebacks::total 94969 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 75966 # Transaction distribution
-system.membus.trans_dist::ReadResp 75966 # Transaction distribution
-system.membus.trans_dist::WriteReq 30891 # Transaction distribution
-system.membus.trans_dist::WriteResp 30891 # Transaction distribution
-system.membus.trans_dist::Writeback 131104 # Transaction distribution
+system.membus.trans_dist::ReadReq 75988 # Transaction distribution
+system.membus.trans_dist::ReadResp 75988 # Transaction distribution
+system.membus.trans_dist::WriteReq 30846 # Transaction distribution
+system.membus.trans_dist::WriteResp 30846 # Transaction distribution
+system.membus.trans_dist::Writeback 131159 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 60393 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40881 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15635 # Transaction distribution
-system.membus.trans_dist::ReadExReq 196339 # Transaction distribution
-system.membus.trans_dist::ReadExResp 152220 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60361 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40906 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15595 # Transaction distribution
+system.membus.trans_dist::ReadExReq 196283 # Transaction distribution
+system.membus.trans_dist::ReadExResp 152192 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107876 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652208 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 773592 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652086 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 773470 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109142 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109142 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 882734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 882612 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162766 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17902820 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18092602 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17906316 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18096098 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4650624 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4650624 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22743226 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 22746722 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 496901 # Request fanout histogram
+system.membus.snoop_fanout::samples 571767 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 496901 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 571767 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 496901 # Request fanout histogram
+system.membus.snoop_fanout::total 571767 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 305006 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 305006 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30891 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30891 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 225951 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 40955 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 101503 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 305452 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 305452 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30846 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30846 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 226118 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 60537 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40981 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 101518 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 213786 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 213786 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117662 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410661 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1528323 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664008 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10429874 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 45093882 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1118722 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410600 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1529322 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34707388 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10425906 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 45133294 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 36713 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 838716 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.043490 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.203958 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 914196 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.039900 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.195723 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 802240 95.65% 95.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 877720 96.01% 96.01% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36476 3.99% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 838716 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 914196 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1378466 # Simulator instruction rate (inst/s)
-host_op_rate 1678062 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26878113924 # Simulator tick rate (ticks/s)
-host_mem_usage 614624 # Number of bytes of host memory used
-host_seconds 103.57 # Real time elapsed on the host
+host_inst_rate 1032026 # Simulator instruction rate (inst/s)
+host_op_rate 1256326 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20123025378 # Simulator tick rate (ticks/s)
+host_mem_usage 560940 # Number of bytes of host memory used
+host_seconds 138.34 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 74000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205239845 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 36631 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3268658 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011156 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.105030 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3336291 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.019237 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.137356 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3232194 98.88% 98.88% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 36464 1.12% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3272112 98.08% 98.08% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 64179 1.92% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3268658 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3336291 # Request fanout histogram
system.iobus.trans_dist::ReadReq 30164 # Transaction distribution
system.iobus.trans_dist::ReadResp 30164 # Transaction distribution
system.iobus.trans_dist::WriteReq 59002 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22909145 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 359045 # Request fanout histogram
+system.membus.snoop_fanout::samples 426678 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 359045 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 426678 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 359045 # Request fanout histogram
+system.membus.snoop_fanout::total 426678 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
---------- Begin Simulation Statistics ----------
-sim_seconds 2.868581 # Number of seconds simulated
-sim_ticks 2868581440500 # Number of ticks simulated
-final_tick 2868581440500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.868578 # Number of seconds simulated
+sim_ticks 2868577613500 # Number of ticks simulated
+final_tick 2868577613500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 717360 # Simulator instruction rate (inst/s)
-host_op_rate 867708 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15647358559 # Simulator tick rate (ticks/s)
-host_mem_usage 639748 # Number of bytes of host memory used
-host_seconds 183.33 # Real time elapsed on the host
-sim_insts 131511324 # Number of instructions simulated
-sim_ops 159074269 # Number of ops (including micro ops) simulated
+host_inst_rate 558438 # Simulator instruction rate (inst/s)
+host_op_rate 675477 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 12195118142 # Simulator tick rate (ticks/s)
+host_mem_usage 590596 # Number of bytes of host memory used
+host_seconds 235.22 # Real time elapsed on the host
+sim_insts 131357672 # Number of instructions simulated
+sim_ops 158887964 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 384 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1161572 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1227520 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 8321088 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 141140 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 467936 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 345792 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1167908 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1250980 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 8365696 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 137236 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 508432 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 356544 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11666584 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1161572 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 141140 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1302712 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8208384 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
+system.physmem.bytes_read::total 11788332 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1167908 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 137236 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1305144 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8293056 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8226128 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8310620 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 6 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 26603 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 19706 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 130017 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2360 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 7335 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 5403 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 26702 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 20066 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 130714 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2299 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 7964 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 5571 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 191448 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 128256 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 193340 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 129579 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 132692 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 156 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 133970 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 134 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 404929 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 427919 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 2900768 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 49202 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 163125 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 120545 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 407138 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 436098 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 2916322 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 47841 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 177242 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 124293 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4067022 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 404929 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 49202 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 454131 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2861478 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 6172 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4109469 # Total read bandwidth from this memory (bytes/s)
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+system.physmem.bw_inst_read::total 454979 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2890999 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data 6109 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2867664 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2861478 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 156 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2897122 # Write bandwidth from this memory (bytes/s)
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+system.physmem.bw_total::cpu0.dtb.walker 134 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 404929 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 434091 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 2900768 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 49202 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 163138 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 120545 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu0.data 442207 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 2916322 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
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+system.physmem.bw_total::cpu1.data 177256 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::realview.ide 335 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6934686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 191448 # Number of read requests accepted
-system.physmem.writeReqs 168916 # Number of write requests accepted
-system.physmem.readBursts 191448 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 168916 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 12244160 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 8512 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9286016 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 11666584 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 10544464 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 133 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 23799 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 13043 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 11402 # Per bank write bursts
-system.physmem.perBankRdBursts::1 11523 # Per bank write bursts
-system.physmem.perBankRdBursts::2 11617 # Per bank write bursts
-system.physmem.perBankRdBursts::3 11771 # Per bank write bursts
-system.physmem.perBankRdBursts::4 20348 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12097 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11123 # Per bank write bursts
-system.physmem.perBankRdBursts::7 11241 # Per bank write bursts
-system.physmem.perBankRdBursts::8 11419 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11532 # Per bank write bursts
-system.physmem.perBankRdBursts::10 11480 # Per bank write bursts
-system.physmem.perBankRdBursts::11 10715 # Per bank write bursts
-system.physmem.perBankRdBursts::12 11252 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11225 # Per bank write bursts
-system.physmem.perBankRdBursts::14 11052 # Per bank write bursts
-system.physmem.perBankRdBursts::15 11518 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9249 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9496 # Per bank write bursts
-system.physmem.perBankWrBursts::2 9535 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9435 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8870 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9467 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9116 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8737 # Per bank write bursts
-system.physmem.perBankWrBursts::8 8796 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9230 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9164 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8822 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9029 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8642 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8756 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8750 # Per bank write bursts
+system.physmem.bw_total::total 7006592 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 193340 # Number of read requests accepted
+system.physmem.writeReqs 170194 # Number of write requests accepted
+system.physmem.readBursts 193340 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 170194 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 12365312 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 8448 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9398080 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 11788332 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 10628956 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 132 # Number of DRAM read bursts serviced by the write queue
+system.physmem.mergedWrBursts 23320 # Number of DRAM write bursts merged with an existing one
+system.physmem.neitherReadNorWriteReqs 12970 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 11741 # Per bank write bursts
+system.physmem.perBankRdBursts::1 11572 # Per bank write bursts
+system.physmem.perBankRdBursts::2 11914 # Per bank write bursts
+system.physmem.perBankRdBursts::3 12194 # Per bank write bursts
+system.physmem.perBankRdBursts::4 20279 # Per bank write bursts
+system.physmem.perBankRdBursts::5 11715 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11292 # Per bank write bursts
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+system.physmem.perBankRdBursts::9 12328 # Per bank write bursts
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+system.physmem.perBankRdBursts::14 10907 # Per bank write bursts
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+system.physmem.perBankWrBursts::4 8974 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 8686 # Per bank write bursts
+system.physmem.perBankWrBursts::15 8539 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 83 # Number of times write queue was full causing retry
-system.physmem.totGap 2868581033500 # Total gap between requests
+system.physmem.numWrRetry 53 # Number of times write queue was full causing retry
+system.physmem.totGap 2868577154000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 9742 # Read request sizes (log2)
+system.physmem.readPktSize::2 9731 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 181678 # Read request sizes (log2)
+system.physmem.readPktSize::6 183581 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 4436 # Write request sizes (log2)
+system.physmem.writePktSize::2 4391 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 164480 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 134188 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 15248 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::10 74 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::56 204 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 184 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 132 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 171 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::61 126 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 110 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 200 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 81717 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 263.471640 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 146.531290 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 321.110863 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 41089 50.28% 50.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 16342 20.00% 70.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5746 7.03% 77.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3516 4.30% 81.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2447 2.99% 84.61% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1416 1.73% 86.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 997 1.22% 87.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 891 1.09% 88.65% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 9273 11.35% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 81717 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 5972 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 32.034494 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 599.214233 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 5970 99.97% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 5972 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 5972 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 24.295713 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.853114 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 39.858214 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-31 5595 93.69% 93.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-47 97 1.62% 95.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-63 24 0.40% 95.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-79 14 0.23% 95.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-95 35 0.59% 96.53% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-111 43 0.72% 97.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-127 25 0.42% 97.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-143 12 0.20% 97.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-159 18 0.30% 98.17% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::160-175 5 0.08% 98.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-191 30 0.50% 98.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-207 15 0.25% 99.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::208-223 7 0.12% 99.13% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::224-239 4 0.07% 99.20% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::240-255 3 0.05% 99.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::256-271 1 0.02% 99.26% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::272-287 3 0.05% 99.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::288-303 3 0.05% 99.36% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::304-319 7 0.12% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::320-335 2 0.03% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::336-351 6 0.10% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::352-367 7 0.12% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::368-383 1 0.02% 99.75% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::384-399 2 0.03% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::400-415 1 0.02% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::464-479 1 0.02% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::480-495 3 0.05% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::496-511 1 0.02% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::512-527 1 0.02% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::528-543 3 0.05% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::544-559 1 0.02% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::560-575 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 5972 # Writes before turning the bus around for reads
-system.physmem.totQLat 4538980935 # Total ticks spent queuing
-system.physmem.totMemAccLat 8126137185 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 956575000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 23725.17 # Average queueing delay per DRAM burst
+system.physmem.wrQLenPdf::15 2106 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::63 90 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 83936 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 259.284788 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 144.169379 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 318.901486 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 42814 51.01% 51.01% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 16839 20.06% 71.07% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5671 6.76% 77.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3554 4.23% 82.06% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2350 2.80% 84.86% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1452 1.73% 86.59% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1048 1.25% 87.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 956 1.14% 88.98% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 9252 11.02% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 83936 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6009 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 32.152937 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 562.980980 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6006 99.95% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::2048-4095 2 0.03% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 6009 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6009 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 24.437510 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.815074 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 42.361816 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-31 5653 94.08% 94.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-47 88 1.46% 95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-63 21 0.35% 95.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-79 11 0.18% 96.07% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-95 30 0.50% 96.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-111 35 0.58% 97.15% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-127 32 0.53% 97.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-143 15 0.25% 97.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-159 11 0.18% 98.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::160-175 9 0.15% 98.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::176-191 22 0.37% 98.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::192-207 19 0.32% 98.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::208-223 8 0.13% 99.08% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::224-239 2 0.03% 99.12% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::240-255 4 0.07% 99.18% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::256-271 3 0.05% 99.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::272-287 3 0.05% 99.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::288-303 2 0.03% 99.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::304-319 5 0.08% 99.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::320-335 5 0.08% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::336-351 6 0.10% 99.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::352-367 6 0.10% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::368-383 1 0.02% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::384-399 2 0.03% 99.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::416-431 1 0.02% 99.75% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::432-447 2 0.03% 99.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::480-495 1 0.02% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::496-511 4 0.07% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::512-527 2 0.03% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::528-543 2 0.03% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::656-671 1 0.02% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::736-751 1 0.02% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6009 # Writes before turning the bus around for reads
+system.physmem.totQLat 4585121898 # Total ticks spent queuing
+system.physmem.totMemAccLat 8207771898 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 966040000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 23731.53 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 42475.17 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.27 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 3.24 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 4.07 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.68 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 42481.53 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.31 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 3.28 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 4.11 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.71 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.09 # Average write queue length when enqueuing
-system.physmem.readRowHits 160412 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94279 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 83.85 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 64.97 # Row buffer hit rate for writes
-system.physmem.avgGap 7960231.97 # Average gap between requests
-system.physmem.pageHitRate 75.70 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 319183200 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 174157500 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 788743800 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 478904400 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 83526196590 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1647879002250 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1920527828700 # Total energy per rank (pJ)
-system.physmem_0.averagePower 669.504870 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2741264066617 # Time in different power states
-system.physmem_0.memoryStateTime::REF 95788160000 # Time in different power states
+system.physmem.avgRdQLen 1.09 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 25.78 # Average write queue length when enqueuing
+system.physmem.readRowHits 161661 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94455 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 83.67 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 64.31 # Row buffer hit rate for writes
+system.physmem.avgGap 7890808.44 # Average gap between requests
+system.physmem.pageHitRate 75.31 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 329026320 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 179528250 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 798891600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 486116640 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 84057386715 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1647408374250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1920620456175 # Total energy per rank (pJ)
+system.physmem_0.averagePower 669.538978 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2740481725360 # Time in different power states
+system.physmem_0.memoryStateTime::REF 95787900000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31529102383 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 32307893640 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 298597320 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 162925125 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 703505400 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 461304720 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 187361640960 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 82377359595 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1648886754000 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1920252087120 # Total energy per rank (pJ)
-system.physmem_1.averagePower 669.408745 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2742945725805 # Time in different power states
-system.physmem_1.memoryStateTime::REF 95788160000 # Time in different power states
+system.physmem_1.actEnergy 305529840 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 166707750 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 708123000 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 465438960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 187361132400 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 82818901260 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1648494765000 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1920320598210 # Total energy per rank (pJ)
+system.physmem_1.averagePower 669.434445 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2742293590423 # Time in different power states
+system.physmem_1.memoryStateTime::REF 95787900000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 29845454195 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 30490063327 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 7634 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 7634 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1372 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6262 # Level at which table walker walks with short descriptors terminate
-system.cpu0.dtb.walker.walkWaitTime::samples 7634 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 7634 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 7634 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkCompletionTime::samples 6240 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::mean 9567.588141 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::gmean 8440.173252 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::stdev 5686.595019 # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::0-16383 6084 97.50% 97.50% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::16384-32767 143 2.29% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::32768-49151 8 0.13% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::81920-98303 3 0.05% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walks 7618 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 7618 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 1341 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 6277 # Level at which table walker walks with short descriptors terminate
+system.cpu0.dtb.walker.walkWaitTime::samples 7618 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 7618 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 7618 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkCompletionTime::samples 6224 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::mean 9157.575514 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::gmean 8041.236075 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::stdev 5531.388532 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::0-16383 6077 97.64% 97.64% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::16384-32767 137 2.20% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.10% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::49152-65535 1 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu0.dtb.walker.walkCompletionTime::total 6240 # Table walker service (enqueue to completion) latency
+system.cpu0.dtb.walker.walkCompletionTime::total 6224 # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 1121059000 # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0 1121059000 100.00% 100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 1121059000 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 4907 78.64% 78.64% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1333 21.36% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 6240 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7634 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkPageSizes::4K 4922 79.08% 79.08% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1302 20.92% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 6224 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 7618 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7634 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6240 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 7618 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6224 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6240 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 13874 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6224 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 13842 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 25111402 # DTB read hits
-system.cpu0.dtb.read_misses 6533 # DTB read misses
-system.cpu0.dtb.write_hits 18719047 # DTB write hits
-system.cpu0.dtb.write_misses 1101 # DTB write misses
+system.cpu0.dtb.read_hits 25125547 # DTB read hits
+system.cpu0.dtb.read_misses 6527 # DTB read misses
+system.cpu0.dtb.write_hits 18731781 # DTB write hits
+system.cpu0.dtb.write_misses 1091 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3405 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3404 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1785 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 1741 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 25117935 # DTB read accesses
-system.cpu0.dtb.write_accesses 18720148 # DTB write accesses
+system.cpu0.dtb.read_accesses 25132074 # DTB read accesses
+system.cpu0.dtb.write_accesses 18732872 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 43830449 # DTB hits
-system.cpu0.dtb.misses 7634 # DTB misses
-system.cpu0.dtb.accesses 43838083 # DTB accesses
+system.cpu0.dtb.hits 43857328 # DTB hits
+system.cpu0.dtb.misses 7618 # DTB misses
+system.cpu0.dtb.accesses 43864946 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkWaitTime::0 3348 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total 3348 # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples 2332 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::mean 9914.451115 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::gmean 8640.132285 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::stdev 5844.480359 # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::0-8191 848 36.36% 36.36% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::8192-16383 1427 61.19% 97.56% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.68% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::24576-32767 51 2.19% 99.87% # Table walker service (enqueue to completion) latency
-system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::mean 9422.169811 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::gmean 8126.335555 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::stdev 5925.919906 # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::0-8191 980 42.02% 42.02% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::8192-16383 1299 55.70% 97.73% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::16384-24575 3 0.13% 97.86% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.93% 99.79% # Table walker service (enqueue to completion) latency
+system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.13% 99.91% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total 2332 # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2332 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2332 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total 5680 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 118783416 # ITB inst hits
+system.cpu0.itb.inst_hits 118901491 # ITB inst hits
system.cpu0.itb.inst_misses 3348 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 118786764 # ITB inst accesses
-system.cpu0.itb.hits 118783416 # DTB hits
+system.cpu0.itb.inst_accesses 118904839 # ITB inst accesses
+system.cpu0.itb.hits 118901491 # DTB hits
system.cpu0.itb.misses 3348 # DTB misses
-system.cpu0.itb.accesses 118786764 # DTB accesses
-system.cpu0.numCycles 5737162881 # number of cpu cycles simulated
+system.cpu0.itb.accesses 118904839 # DTB accesses
+system.cpu0.numCycles 5737155227 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 115118664 # Number of instructions committed
-system.cpu0.committedOps 139117689 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 123147620 # Number of integer alu accesses
+system.cpu0.committedInsts 115236645 # Number of instructions committed
+system.cpu0.committedOps 139243080 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 123236123 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9820 # Number of float alu accesses
-system.cpu0.num_func_calls 12673072 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 15652345 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 123147620 # number of integer instructions
+system.cpu0.num_func_calls 12671679 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 15683932 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 123236123 # number of integer instructions
system.cpu0.num_fp_insts 9820 # number of float instructions
-system.cpu0.num_int_register_reads 226729132 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 85574900 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 226877119 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 85629478 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7560 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 504016583 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 52146919 # number of times the CC registers were written
-system.cpu0.num_mem_refs 44965604 # number of memory refs
-system.cpu0.num_load_insts 25362826 # Number of load instructions
-system.cpu0.num_store_insts 19602778 # Number of store instructions
-system.cpu0.num_idle_cycles 5466015382.984095 # Number of idle cycles
-system.cpu0.num_busy_cycles 271147498.015905 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.047262 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.952738 # Percentage of idle cycles
-system.cpu0.Branches 29061799 # Number of branches fetched
+system.cpu0.num_cc_register_reads 504430555 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 52228186 # number of times the CC registers were written
+system.cpu0.num_mem_refs 44991026 # number of memory refs
+system.cpu0.num_load_insts 25375377 # Number of load instructions
+system.cpu0.num_store_insts 19615649 # Number of store instructions
+system.cpu0.num_idle_cycles 5465784255.910094 # Number of idle cycles
+system.cpu0.num_busy_cycles 271370971.089905 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.047301 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.952699 # Percentage of idle cycles
+system.cpu0.Branches 29094451 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 97796607 68.45% 68.45% # Class of executed instruction
-system.cpu0.op_class::IntMult 109233 0.08% 68.52% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.52% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 8187 0.01% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.53% # Class of executed instruction
-system.cpu0.op_class::MemRead 25362826 17.75% 86.28% # Class of executed instruction
-system.cpu0.op_class::MemWrite 19602778 13.72% 100.00% # Class of executed instruction
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+system.cpu0.op_class::FloatMult 0 0.00% 68.53% # Class of executed instruction
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+system.cpu0.op_class::SimdAddAcc 0 0.00% 68.53% # Class of executed instruction
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 142881904 # Class of executed instruction
+system.cpu0.op_class::total 143005338 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1874 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 688886 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 494.817079 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 42962889 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 689398 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 62.319428 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 1149671500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.817079 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966440 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.966440 # Average percentage of cache occupancy
+system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 691902 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 493.788529 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 42987184 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 692414 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 62.083066 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 1147014500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.788529 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.964431 # Average percentage of cache occupancy
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system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 286 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 116 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 103 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 88293922 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 88293922 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 23854264 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 23854264 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 17989541 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 17989541 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 318725 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 318725 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 364533 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 364533 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361797 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 361797 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 41843805 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 41843805 # number of demand (read+write) hits
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-system.cpu0.dcache.overall_hits::total 42162530 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 393288 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 393288 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 323540 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 323540 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 127427 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 127427 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21927 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 21927 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19722 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 19722 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 716828 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 716828 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 844255 # number of overall misses
-system.cpu0.dcache.overall_misses::total 844255 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5012719236 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5012719236 # number of ReadReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total 5098069375 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 332035250 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 332035250 # number of LoadLockedReq miss cycles
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-system.cpu0.dcache.StoreCondReq_miss_latency::total 435652050 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1835500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1835500 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 10110788611 # number of demand (read+write) miss cycles
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-system.cpu0.dcache.overall_miss_latency::total 10110788611 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 24247552 # number of ReadReq accesses(hits+misses)
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-system.cpu0.dcache.WriteReq_accesses::total 18313081 # number of WriteReq accesses(hits+misses)
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-system.cpu0.dcache.SoftPFReq_accesses::total 446152 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386460 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 386460 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381519 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381519 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 42560633 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 42560633 # number of demand (read+write) accesses
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-system.cpu0.dcache.overall_accesses::total 43006785 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.016220 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.016220 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.017667 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.017667 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.285613 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.285613 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056738 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056738 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051693 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051693 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.016843 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.016843 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.019631 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.019631 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12745.670440 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12745.670440 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15757.153289 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 15757.153289 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15142.757787 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15142.757787 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22089.648616 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22089.648616 # average StoreCondReq miss latency
+system.cpu0.dcache.tags.tag_accesses 88350780 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 88350780 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 23864345 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 23864345 # number of ReadReq hits
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+system.cpu0.dcache.SoftPFReq_hits::total 319294 # number of SoftPFReq hits
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+system.cpu0.dcache.LoadLockedReq_hits::total 365178 # number of LoadLockedReq hits
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+system.cpu0.dcache.overall_hits::total 42185684 # number of overall hits
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+system.cpu0.dcache.ReadReq_misses::total 396651 # number of ReadReq misses
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+system.cpu0.dcache.WriteReq_misses::total 323350 # number of WriteReq misses
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+system.cpu0.dcache.SoftPFReq_misses::total 127092 # number of SoftPFReq misses
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+system.cpu0.dcache.LoadLockedReq_misses::total 21763 # number of LoadLockedReq misses
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+system.cpu0.dcache.ReadReq_miss_latency::total 5048891005 # number of ReadReq miss cycles
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+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330377500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 330377500 # number of LoadLockedReq miss cycles
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12728.799385 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12728.799385 # average ReadReq miss latency
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system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14104.901889 # average overall miss latency
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+system.cpu0.dcache.demand_avg_miss_latency::total 14103.176326 # average overall miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 11987.232875 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 504121 # number of writebacks
-system.cpu0.dcache.writebacks::total 504121 # number of writebacks
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-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15169 # number of LoadLockedReq MSHR hits
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97840500 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_rate::total 0.016249 # mshr miss rate for demand accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11049.886325 # average ReadReq mshr miss latency
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-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15436.256011 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14477.730098 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14477.730098 # average LoadLockedReq mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20570.984180 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 505765 # number of writebacks
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+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224167 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224167 # mshr miss rate for SoftPFReq accesses
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system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total 9865.289794 # average overall miss latency
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system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 802157500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 802157500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 802157500 # number of overall MSHR uncacheable cycles
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+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88911.272445 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu0.l2cache.prefetcher.pfSpanPage 237006 # number of prefetches not generated due to page crossing
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system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 730253500 # number of ReadReq MSHR uncacheable cycles
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system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 730253500 # number of overall MSHR uncacheable cycles
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-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for ReadReq accesses
-system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for ReadReq accesses
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system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.480767 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.480767 # mshr miss rate for UpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.911032 # mshr miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.911032 # mshr miss rate for SCUpgradeReq accesses
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system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.158963 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.158963 # mshr miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184042 # mshr miss rate for demand accesses
-system.cpu0.l2cache.demand_mshr_miss_rate::total 0.099287 # mshr miss rate for demand accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.026968 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.034991 # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042796 # mshr miss rate for overall accesses
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system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
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-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22742.345957 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 29542.690680 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55320.103445 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19621.173082 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19621.173082 # average UpgradeReq mshr miss latency
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-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14375.037581 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 192571 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192571 # average SCUpgradeFailReq mshr miss latency
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-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 36152.288892 # average ReadExReq mshr miss latency
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-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 26931.870209 # average overall mshr miss latency
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-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16900.224215 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16304.511278 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43223.634347 # average overall mshr miss latency
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-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55320.103445 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 44881.149122 # average overall mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55085.343530 # average HardPFReq mshr miss latency
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+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19528.282560 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14419.048160 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14419.048160 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 189099.600000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 189099.600000 # average SCUpgradeFailReq mshr miss latency
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+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43450.370088 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27091.512404 # average overall mshr miss latency
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+system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 162617.510722 # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1733379 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1686259 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28500 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28500 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 504119 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 307885 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 88136 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42217 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 111625 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 297195 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 284749 # Transaction distribution
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-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2362865 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10199 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 22165 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4616933 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 70553208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 84179104 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 15204 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 33076 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 154780592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 633519 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 2968459 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 3.176473 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.381222 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 1738254 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1687491 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28452 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 505760 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 309559 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 88185 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42256 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 111549 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 50 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 297072 # Transaction distribution
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+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13944 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 30948 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 154949960 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 641653 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3048291 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 1.181009 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.385025 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 2444606 82.35% 82.35% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 523853 17.65% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 2496524 81.90% 81.90% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 551767 18.10% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2968459 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1775328997 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 3048291 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1778395498 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 114507000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 114075998 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1667097754 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1664668023 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1206509407 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1210905566 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy 6398000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 13896250 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 13895250 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 3283 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 3283 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 611 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2672 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walkWaitTime::samples 3283 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 3283 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 3283 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 2513 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 9027.258257 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 8086.769918 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 4736.776885 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-4095 485 19.30% 19.30% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-8191 533 21.21% 40.51% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::8192-12287 1045 41.58% 82.09% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-16383 324 12.89% 94.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::16384-20479 44 1.75% 96.74% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::20480-24575 19 0.76% 97.49% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::24576-28671 51 2.03% 99.52% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::28672-32767 8 0.32% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::36864-40959 3 0.12% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::45056-49151 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 2513 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1651557968 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1651557968 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1651557968 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 1910 76.00% 76.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 603 24.00% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 2513 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3283 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 3295 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 3295 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 601 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 2694 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 3295 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 3295 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 3295 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 2525 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 9355.742574 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 8433.023249 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 5123.717679 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-8191 905 35.84% 35.84% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1497 59.29% 95.13% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::16384-24575 62 2.46% 97.58% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::24576-32767 54 2.14% 99.72% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.08% 99.80% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::40960-49151 4 0.16% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 2525 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1642630968 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1642630968 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1642630968 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1932 76.51% 76.51% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 593 23.49% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 2525 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 3295 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3283 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2513 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 3295 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2525 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2513 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 5796 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2525 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 5820 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3974119 # DTB read hits
-system.cpu1.dtb.read_misses 2776 # DTB read misses
-system.cpu1.dtb.write_hits 3444686 # DTB write hits
-system.cpu1.dtb.write_misses 507 # DTB write misses
+system.cpu1.dtb.read_hits 3921520 # DTB read hits
+system.cpu1.dtb.read_misses 2787 # DTB read misses
+system.cpu1.dtb.write_hits 3403460 # DTB write hits
+system.cpu1.dtb.write_misses 508 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 2006 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 362 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 344 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3976895 # DTB read accesses
-system.cpu1.dtb.write_accesses 3445193 # DTB write accesses
+system.cpu1.dtb.read_accesses 3924307 # DTB read accesses
+system.cpu1.dtb.write_accesses 3403968 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 7418805 # DTB hits
-system.cpu1.dtb.misses 3283 # DTB misses
-system.cpu1.dtb.accesses 7422088 # DTB accesses
+system.cpu1.dtb.hits 7324980 # DTB hits
+system.cpu1.dtb.misses 3295 # DTB misses
+system.cpu1.dtb.accesses 7328275 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkWaitTime::0 1740 100.00% 100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total 1740 # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples 1101 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 9655.767484 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 8490.755174 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 5670.300287 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-4095 219 19.89% 19.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-8191 163 14.80% 34.70% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::8192-12287 463 42.05% 76.75% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.28% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.37% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::24576-28671 25 2.27% 97.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::28672-32767 21 1.91% 99.55% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.27% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 9831.970936 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 8728.225186 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 5541.612386 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-4095 184 16.71% 16.71% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-8191 162 14.71% 31.43% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::8192-12287 497 45.14% 76.57% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-16383 204 18.53% 95.10% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::16384-20479 1 0.09% 95.19% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 95.28% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::24576-28671 28 2.54% 97.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::28672-32767 19 1.73% 99.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::36864-40959 3 0.27% 99.82% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total 1101 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1651010968 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1651010968 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1651010968 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::samples 1642083968 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1642083968 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1642083968 # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K 937 85.10% 85.10% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::1M 164 14.90% 100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total 1101 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1101 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1101 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total 2841 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 16749094 # ITB inst hits
+system.cpu1.itb.inst_hits 16475856 # ITB inst hits
system.cpu1.itb.inst_misses 1740 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 16750834 # ITB inst accesses
-system.cpu1.itb.hits 16749094 # DTB hits
+system.cpu1.itb.inst_accesses 16477596 # ITB inst accesses
+system.cpu1.itb.hits 16475856 # DTB hits
system.cpu1.itb.misses 1740 # DTB misses
-system.cpu1.itb.accesses 16750834 # DTB accesses
-system.cpu1.numCycles 5736248293 # number of cpu cycles simulated
+system.cpu1.itb.accesses 16477596 # DTB accesses
+system.cpu1.numCycles 5736236800 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 16392660 # Number of instructions committed
-system.cpu1.committedOps 19956580 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 17976734 # Number of integer alu accesses
+system.cpu1.committedInsts 16121027 # Number of instructions committed
+system.cpu1.committedOps 19644884 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 17715670 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1857 # Number of float alu accesses
-system.cpu1.num_func_calls 1033061 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1853914 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 17976734 # number of integer instructions
+system.cpu1.num_func_calls 1024357 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 1805296 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 17715670 # number of integer instructions
system.cpu1.num_fp_insts 1857 # number of float instructions
-system.cpu1.num_int_register_reads 32611379 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 12600410 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 32157611 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 12423544 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1341 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 72918750 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 6543930 # number of times the CC registers were written
-system.cpu1.num_mem_refs 7653523 # number of memory refs
-system.cpu1.num_load_insts 4085696 # Number of load instructions
-system.cpu1.num_store_insts 3567827 # Number of store instructions
-system.cpu1.num_idle_cycles 5685220667.433728 # Number of idle cycles
-system.cpu1.num_busy_cycles 51027625.566272 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.008896 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.991104 # Percentage of idle cycles
-system.cpu1.Branches 2968133 # Number of branches fetched
+system.cpu1.num_cc_register_reads 71811842 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 6390929 # number of times the CC registers were written
+system.cpu1.num_mem_refs 7557236 # number of memory refs
+system.cpu1.num_load_insts 4032278 # Number of load instructions
+system.cpu1.num_store_insts 3524958 # Number of store instructions
+system.cpu1.num_idle_cycles 5685648636.968273 # Number of idle cycles
+system.cpu1.num_busy_cycles 50588163.031727 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.008819 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.991181 # Percentage of idle cycles
+system.cpu1.Branches 2908306 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 12626391 62.17% 62.17% # Class of executed instruction
-system.cpu1.op_class::IntMult 25909 0.13% 62.30% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 62.30% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 3321 0.02% 62.32% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 62.32% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 62.32% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 62.32% # Class of executed instruction
-system.cpu1.op_class::MemRead 4085696 20.12% 82.43% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3567827 17.57% 100.00% # Class of executed instruction
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+system.cpu1.op_class::IntMult 25890 0.13% 62.19% # Class of executed instruction
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+system.cpu1.op_class::FloatAdd 0 0.00% 62.19% # Class of executed instruction
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+system.cpu1.op_class::FloatMult 0 0.00% 62.19% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 62.19% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 62.19% # Class of executed instruction
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+system.cpu1.op_class::SimdCvt 0 0.00% 62.19% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 62.19% # Class of executed instruction
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 20309210 # Class of executed instruction
+system.cpu1.op_class::total 19994333 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu1.dcache.tags.replacements 187627 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 465.215072 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 7146939 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 187994 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 38.016846 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 104853894000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 465.215072 # Average occupied blocks per requestor
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-system.cpu1.dcache.tags.occ_percent::total 0.908623 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 367 # Occupied blocks per task id
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-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 52 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.716797 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 15057330 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 15057330 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 3659340 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3659340 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 3255921 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3255921 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49714 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 49714 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79782 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 79782 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71812 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 71812 # number of StoreCondReq hits
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-system.cpu1.dcache.demand_hits::total 6915261 # number of demand (read+write) hits
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-system.cpu1.dcache.overall_hits::total 6964975 # number of overall hits
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-system.cpu1.dcache.ReadReq_misses::total 134401 # number of ReadReq misses
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-system.cpu1.dcache.WriteReq_misses::total 90853 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30496 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 30496 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17326 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23466 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23466 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 225254 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 225254 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 255750 # number of overall misses
-system.cpu1.dcache.overall_misses::total 255750 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1931922000 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 1931922000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2253615359 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2253615359 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 317972750 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 317972750 # number of LoadLockedReq miss cycles
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-system.cpu1.dcache.StoreCondReq_miss_latency::total 552026738 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2980000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2980000 # number of StoreCondFailReq miss cycles
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-system.cpu1.dcache.overall_miss_latency::total 4185537359 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 3793741 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.178420 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14374.312691 # average ReadReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23524.534987 # average StoreCondReq miss latency
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+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.384268 # miss rate for SoftPFReq accesses
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+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180597 # miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250881 # miss rate for StoreCondReq accesses
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+system.cpu1.dcache.demand_miss_rate::total 0.031710 # miss rate for demand accesses
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+system.cpu1.dcache.overall_miss_rate::total 0.035606 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14483.755853 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14483.755853 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25383.770596 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 25383.770596 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18563.449936 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18563.449936 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23544.623771 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23544.623771 # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18581.411913 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18581.411913 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16365.737474 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 16365.737474 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18893.348708 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18893.348708 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16639.735666 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 16639.735666 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 117066 # number of writebacks
-system.cpu1.dcache.writebacks::total 117066 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 249 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 249 # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12071 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12071 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 249 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 249 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 249 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 249 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 134152 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 134152 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90853 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 90853 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29793 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 29793 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5255 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5255 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23466 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23466 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 225005 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 225005 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 254798 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 254798 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1724213250 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1724213250 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2112235141 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2112235141 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 459472252 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 459472252 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 82571000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 82571000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 515647762 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 515647762 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2900500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2900500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3836448391 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 3836448391 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4295920643 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4295920643 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406973750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406973750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 280407500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 280407500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 687381250 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 687381250 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035361 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035361 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027146 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027146 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.371437 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.371437 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054115 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054115 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.246290 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246290 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031511 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.031511 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035287 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.035287 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12852.683896 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12852.683896 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23248.931142 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23248.931142 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15422.154600 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15422.154600 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15712.844910 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15712.844910 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21974.250490 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21974.250490 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 114520 # number of writebacks
+system.cpu1.dcache.writebacks::total 114520 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 275 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12066 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12066 # number of LoadLockedReq MSHR hits
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+system.cpu1.dcache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
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+system.cpu1.dcache.overall_mshr_hits::total 275 # number of overall MSHR hits
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+system.cpu1.dcache.ReadReq_mshr_misses::total 132866 # number of ReadReq MSHR misses
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+system.cpu1.dcache.SoftPFReq_mshr_misses::total 29572 # number of SoftPFReq MSHR misses
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+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5172 # number of LoadLockedReq MSHR misses
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+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23491 # number of StoreCondReq MSHR misses
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+system.cpu1.dcache.demand_mshr_misses::total 223322 # number of demand (read+write) MSHR misses
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+system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3084 # number of ReadReq MSHR uncacheable
+system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3084 # number of ReadReq MSHR uncacheable
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+system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2437 # number of WriteReq MSHR uncacheable
+system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5521 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5521 # number of overall MSHR uncacheable misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1717533750 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1717533750 # number of ReadReq MSHR miss cycles
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+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2155103647 # number of WriteReq MSHR miss cycles
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84734500 # number of LoadLockedReq MSHR miss cycles
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+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 516677243 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2366000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2366000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3872637397 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 3872637397 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4344942162 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4344942162 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 406850750 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 406850750 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 279944500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279944500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 686795250 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 686795250 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035486 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035486 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027351 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027351 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.375246 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.375246 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054185 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054185 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250881 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250881 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031671 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.031671 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035468 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.035468 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12926.811600 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12926.811600 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23824.883336 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23824.883336 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15971.350095 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15971.350095 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16383.313998 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16383.313998 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.689158 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.689158 # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17050.502838 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17050.502838 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16860.103466 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16860.103466 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17341.047443 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17341.047443 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17180.882749 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17180.882749 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131923.070687 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 131923.070687 # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 114872.589249 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 114872.589249 # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 124396.893679 # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 124396.893679 # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.icache.tags.replacements 506368 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.574535 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 16242209 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 506880 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 32.043499 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 84702777500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.574535 # Average occupied blocks per requestor
-system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973778 # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total 0.973778 # Average percentage of cache occupancy
+system.cpu1.icache.tags.replacements 502966 # number of replacements
+system.cpu1.icache.tags.tagsinuse 498.575795 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 15972373 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 503478 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 31.724073 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 84694032500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.575795 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973781 # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total 0.973781 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 388 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 121 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 34005058 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 34005058 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 16242209 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 16242209 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 16242209 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 16242209 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::cpu1.inst 16242209 # number of overall hits
-system.cpu1.icache.overall_hits::total 16242209 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 506880 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 506880 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 506880 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 506880 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 506880 # number of overall misses
-system.cpu1.icache.overall_misses::total 506880 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 4441098014 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 4441098014 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 4441098014 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 4441098014 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 4441098014 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 4441098014 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 16749089 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 16749089 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 16749089 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 16749089 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 16749089 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 16749089 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.030263 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.030263 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.030263 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.030263 # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::cpu1.inst 0.030263 # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total 0.030263 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8761.635918 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8761.635918 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8761.635918 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8761.635918 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8761.635918 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 33455180 # Number of tag accesses
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+system.cpu1.icache.overall_hits::total 15972373 # number of overall hits
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+system.cpu1.icache.ReadReq_misses::total 503478 # number of ReadReq misses
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+system.cpu1.icache.demand_misses::total 503478 # number of demand (read+write) misses
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+system.cpu1.icache.overall_misses::total 503478 # number of overall misses
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+system.cpu1.icache.ReadReq_miss_latency::total 4406075262 # number of ReadReq miss cycles
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+system.cpu1.icache.demand_miss_latency::total 4406075262 # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst 4406075262 # number of overall miss cycles
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+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8751.276644 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8751.276644 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8751.276644 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8751.276644 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8751.276644 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3933409986 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3933409986 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3933409986 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15446750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15446750 # number of overall MSHR uncacheable cycles
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-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.030263 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.030263 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 7760.041797 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7760.041797 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 7760.041797 # average overall mshr miss latency
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+system.cpu1.icache.ReadReq_mshr_uncacheable::total 177 # number of ReadReq MSHR uncacheable
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+system.cpu1.icache.overall_mshr_uncacheable_misses::total 177 # number of overall MSHR uncacheable misses
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+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15252750 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15252750 # number of overall MSHR uncacheable cycles
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average ReadReq mshr miss latency
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+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 7749.692614 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 7749.692614 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 7749.692614 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814 # average ReadReq mshr uncacheable latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86173.728814 # average overall mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86173.728814 # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.l2cache.prefetcher.pfIdentified 194618 # number of prefetch candidates identified
-system.cpu1.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue
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+system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
-system.cpu1.l2cache.prefetcher.pfSpanPage 58318 # number of prefetches not generated due to page crossing
-system.cpu1.l2cache.tags.replacements 39568 # number of replacements
-system.cpu1.l2cache.tags.tagsinuse 14853.795199 # Cycle average of tags in use
-system.cpu1.l2cache.tags.total_refs 710508 # Total number of references to valid blocks.
-system.cpu1.l2cache.tags.sampled_refs 54174 # Sample count of references to valid blocks.
-system.cpu1.l2cache.tags.avg_refs 13.115295 # Average number of references to valid blocks.
+system.cpu1.l2cache.prefetcher.pfSpanPage 57534 # number of prefetches not generated due to page crossing
+system.cpu1.l2cache.tags.replacements 39835 # number of replacements
+system.cpu1.l2cache.tags.tagsinuse 14698.947760 # Cycle average of tags in use
+system.cpu1.l2cache.tags.total_refs 703731 # Total number of references to valid blocks.
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+system.cpu1.l2cache.tags.avg_refs 12.934805 # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3300.044649 # Average occupied blocks per requestor
-system.cpu1.l2cache.tags.occ_blocks::cpu1.data 1917.167815 # Average occupied blocks per requestor
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-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 278111.111111 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 28967.204738 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 28967.204738 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20694.834000 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13470.219436 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13595.505618 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29045.807220 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19642.516463 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31238.473506 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 22439.264722 # average overall mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.185238 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15203.520159 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 17407.869349 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 33326.302109 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15746.097009 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15746.097009 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15070.959850 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15070.959850 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 202850 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 202850 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30229.576224 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30229.576224 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 21217.453372 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13761.792453 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13494.382022 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28951.447685 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 20267.625828 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 33326.302109 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23191.967716 # average overall mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 123920.719844 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 121441.045692 # average ReadReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 107372.589249 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 107372.589249 # average WriteReq mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78235.875706 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 116616.283282 # average overall mshr uncacheable latency
+system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 115424.052299 # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1026038 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 726618 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2443 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2443 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 117066 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 27637 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 75553 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41371 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 85405 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 63 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 84221 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 66421 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1014114 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 770781 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5251 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9223 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 1799369 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32441028 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25029390 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7740 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13072 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 57491230 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 567913 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1404964 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 3.347502 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.476177 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 1060646 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 722071 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2437 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 114520 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 27384 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 75380 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41410 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 85537 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 84086 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 66129 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1007310 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 764894 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5302 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9429 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 1786935 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 32223300 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24770860 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7944 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13760 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 57015864 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 636167 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1470628 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 1.384445 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.486464 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 916736 65.25% 65.25% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 488228 34.75% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 905253 61.56% 61.56% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 565375 38.44% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1404964 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 579509000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1470628 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 573017999 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 80431999 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 81259000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 760939764 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 755831512 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 380431845 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 377529095 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy 3316000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 5955000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 5989250 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.trans_dist::ReadReq 31015 # Transaction distribution
system.iobus.trans_dist::ReadResp 31015 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59423 # Transaction distribution
-system.iobus.trans_dist::WriteResp 23199 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59422 # Transaction distribution
+system.iobus.trans_dist::WriteResp 23198 # Transaction distribution
system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56604 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180876 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71548 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162798 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484070 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40093000 # Layer occupancy (ticks)
+system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 198981721 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 199086925 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84719000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36787516 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 36785519 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36445 # number of replacements
-system.iocache.tags.tagsinuse 14.385318 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 14.391068 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 288337625000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.385318 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.899082 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.899082 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 288263513000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.391068 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.899442 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.899442 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 255 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 255 # number of overall misses
system.iocache.overall_misses::total 255 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 32669377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 32669377 # number of ReadReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6649988828 # number of WriteInvalidateReq miss cycles
-system.iocache.WriteInvalidateReq_miss_latency::total 6649988828 # number of WriteInvalidateReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 32669377 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 32669377 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 32669377 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 32669377 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 32671377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 32671377 # number of ReadReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655899029 # number of WriteInvalidateReq miss cycles
+system.iocache.WriteInvalidateReq_miss_latency::total 6655899029 # number of WriteInvalidateReq miss cycles
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+system.iocache.demand_miss_latency::total 32671377 # number of demand (read+write) miss cycles
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-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66035.714286 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65291.666667 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68265.422333 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75486.277254 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85428.867784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70204.097039 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68550.330925 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 101473.138812 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 82323.775633 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 68355.090518 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75041.905525 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 85268.051435 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83750 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70284.442362 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70867.323659 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 104090.239993 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 82315.618920 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 166987.993706 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104443.668831 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 140460.599492 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143321.488823 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 88788.879770 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 139019.116838 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60941.088450 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 155807.636110 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58252.824859 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 97528.548124 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 139866.468516 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 209058 # Transaction distribution
-system.membus.trans_dist::ReadResp 209058 # Transaction distribution
-system.membus.trans_dist::WriteReq 30943 # Transaction distribution
-system.membus.trans_dist::WriteResp 30943 # Transaction distribution
-system.membus.trans_dist::Writeback 128256 # Transaction distribution
+system.membus.trans_dist::ReadReq 210102 # Transaction distribution
+system.membus.trans_dist::ReadResp 210102 # Transaction distribution
+system.membus.trans_dist::WriteReq 30889 # Transaction distribution
+system.membus.trans_dist::WriteResp 30889 # Transaction distribution
+system.membus.trans_dist::Writeback 129579 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40095 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 13060 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 49 # Transaction distribution
-system.membus.trans_dist::ReadExReq 37613 # Transaction distribution
-system.membus.trans_dist::ReadExResp 17283 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
+system.membus.trans_dist::UpgradeReq 77022 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40122 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 12986 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 33 # Transaction distribution
+system.membus.trans_dist::ReadExReq 38648 # Transaction distribution
+system.membus.trans_dist::ReadExResp 18121 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13672 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 634735 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 756359 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13636 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 639843 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 761429 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108908 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 108908 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 865267 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162798 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_count::total 870337 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27344 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17575592 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17765802 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27272 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17781832 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17971968 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 22401258 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 125085 # Total snoops (count)
-system.membus.snoop_fanout::samples 484369 # Request fanout histogram
+system.membus.pkt_size::total 22607424 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 125322 # Total snoops (count)
+system.membus.snoop_fanout::samples 562672 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 484369 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 562672 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 484369 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88115000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 562672 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88118500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11464500 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 11425000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1105573957 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 1114763998 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1100453088 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 1110191376 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 37520484 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 37521481 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 476594 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 476579 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30943 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30943 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 220623 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36279 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 80382 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 40416 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 120798 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 107 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 107 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 50330 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 50330 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1064234 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 261111 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1325345 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31566808 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4207570 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 35774378 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 289326 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 860656 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.042449 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.201611 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 475433 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 475418 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 220641 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36266 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 80215 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40509 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 120724 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 82 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 82 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 50702 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 50702 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1061225 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 262179 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1323404 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31467168 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4256160 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 35723328 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 289388 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 934737 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.039071 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.193764 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 824122 95.76% 95.76% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36534 4.24% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 898216 96.09% 96.09% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36521 3.91% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 860656 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 750507689 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 934737 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 749457686 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 360000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 653714719 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 652203239 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 219646363 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 220037759 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 2903547931500 # Number of ticks simulated
final_tick 2903547931500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 732027 # Simulator instruction rate (inst/s)
-host_op_rate 882601 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18897780106 # Simulator tick rate (ticks/s)
-host_mem_usage 614620 # Number of bytes of host memory used
-host_seconds 153.65 # Real time elapsed on the host
+host_inst_rate 571103 # Simulator instruction rate (inst/s)
+host_op_rate 688575 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 14743405801 # Simulator tick rate (ticks/s)
+host_mem_usage 560940 # Number of bytes of host memory used
+host_seconds 196.94 # Real time elapsed on the host
sim_insts 112472279 # Number of instructions simulated
sim_ops 135607130 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.dcache.demand_mshr_misses::total 698894 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 815237 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 815237 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.ReadReq_mshr_uncacheable::total 31138 # number of ReadReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
+system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
+system.cpu.dcache.overall_mshr_uncacheable_misses::total 58727 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5349732750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 5349732750 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12133728492 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_avg_mshr_miss_latency::total 25015.898322 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23249.483022 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23249.483022 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187331.540240 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187331.540240 # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163580.847439 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163580.847439 # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176173.846783 # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176173.846783 # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1698619 # number of replacements
system.cpu.icache.tags.tagsinuse 510.734312 # Cycle average of tags in use
system.cpu.icache.demand_mshr_misses::total 1699137 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 1699137 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 1699137 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
+system.cpu.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
+system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
+system.cpu.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20807922501 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 20807922501 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20807922501 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12246.171145 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12246.171145 # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average ReadReq mshr uncacheable latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75046.303480 # average overall mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.tags.replacements 89783 # number of replacements
system.cpu.l2cache.tags.tagsinuse 64925.975304 # Cycle average of tags in use
system.cpu.l2cache.overall_mshr_misses::cpu.inst 18063 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143288 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 161360 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 9022 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31138 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.ReadReq_mshr_uncacheable::total 40160 # number of ReadReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27589 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27589 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 9022 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58727 # number of overall MSHR uncacheable misses
+system.cpu.l2cache.overall_mshr_uncacheable_misses::total 67749 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 635250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 140500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1231366500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68170.652715 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64481.408045 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64895.601425 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173318.092042 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 147983.478586 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150576.987205 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150576.987205 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60545.084239 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162634.686771 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 149039.616821 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2291655 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2291640 # Transaction distribution
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 27220 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 205335341 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 53413 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3270364 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011159 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.105044 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3338113 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.019032 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.136637 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3233871 98.88% 98.88% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 36493 1.12% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 3274582 98.10% 98.10% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 63531 1.90% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3270364 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3338113 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2348519500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 20374933 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 498 # Total snoops (count)
-system.membus.snoop_fanout::samples 319985 # Request fanout histogram
+system.membus.snoop_fanout::samples 387734 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 319985 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 387734 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 319985 # Request fanout histogram
+system.membus.snoop_fanout::total 387734 # Request fanout histogram
system.membus.reqLayer0.occupancy 90499500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
sim_ticks 2783867052000 # Number of ticks simulated
final_tick 2783867052000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1291395 # Simulator instruction rate (inst/s)
-host_op_rate 1572066 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25180347721 # Simulator tick rate (ticks/s)
-host_mem_usage 616688 # Number of bytes of host memory used
-host_seconds 110.56 # Real time elapsed on the host
+host_inst_rate 898221 # Simulator instruction rate (inst/s)
+host_op_rate 1093441 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17514028577 # Simulator tick rate (ticks/s)
+host_mem_usage 560944 # Number of bytes of host memory used
+host_seconds 158.95 # Real time elapsed on the host
sim_insts 142772879 # Number of instructions simulated
sim_ops 173803124 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size_system.iocache.mem_side::total 4649856 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22908377 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 359033 # Request fanout histogram
+system.membus.snoop_fanout::samples 426666 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 359033 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 426666 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 359033 # Request fanout histogram
+system.membus.snoop_fanout::total 426666 # Request fanout histogram
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83020 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 205267949 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 36631 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3272324 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.011143 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.104971 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3339957 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.020246 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.140841 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3235860 98.89% 98.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 36464 1.11% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3272336 97.98% 97.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 67621 2.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3272324 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3339957 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 2903640922500 # Number of ticks simulated
final_tick 2903640922500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 705602 # Simulator instruction rate (inst/s)
-host_op_rate 850741 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 18218787173 # Simulator tick rate (ticks/s)
-host_mem_usage 616688 # Number of bytes of host memory used
-host_seconds 159.38 # Real time elapsed on the host
+host_inst_rate 541770 # Simulator instruction rate (inst/s)
+host_op_rate 653210 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 13988619879 # Simulator tick rate (ticks/s)
+host_mem_usage 561968 # Number of bytes of host memory used
+host_seconds 207.57 # Real time elapsed on the host
sim_insts 112456119 # Number of instructions simulated
sim_ops 135587804 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu0.dcache.overall_mshr_misses::cpu0.data 404866 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 411608 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 816474 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31142 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 58736 # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2687850000 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 2671783250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5359633250 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21542.085648 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 24325.170689 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 22945.118773 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 181268.674931 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 193354.234894 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187312.231071 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 143051.398911 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 191019.922007 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163557.186345 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 162020.531131 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 192348.149366 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 176152.180945 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.icache.tags.replacements 1701384 # number of replacements
system.cpu0.icache.tags.tagsinuse 510.734068 # Cycle average of tags in use
system.cpu0.icache.overall_mshr_misses::cpu0.inst 856651 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 845251 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 1701902 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.ReadReq_mshr_uncacheable::total 9022 # number of ReadReq MSHR uncacheable
+system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
+system.cpu0.icache.overall_mshr_uncacheable_misses::total 9022 # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10442855002 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10375133501 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 20817988503 # number of ReadReq MSHR miss cycles
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12190.326051 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12274.618428 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.189928 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 75046.303480 # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 75046.303480 # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 75046.303480 # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.l2c.overall_mshr_misses::cpu1.inst 9421 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 79599 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 158027 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 9022 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15569 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 15573 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 40164 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu0.data 15798 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 11796 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 27594 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 9022 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu0.data 31367 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 27369 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 67758 # number of overall MSHR uncacheable misses
system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 223750 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 141000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 574142498 # number of ReadReq MSHR miss cycles
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 67488.164738 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63995.741504 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 64693.110291 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167244.026591 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 179351.891094 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 147970.993925 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 130046.334979 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 178017.166836 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 150553.109372 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60545.084239 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 148509.396818 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 178776.626841 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 149022.543464 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 70492 # Transaction distribution
system.membus.trans_dist::ReadResp 70492 # Transaction distribution
system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 19954937 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 498 # Total snoops (count)
-system.membus.snoop_fanout::samples 313389 # Request fanout histogram
+system.membus.snoop_fanout::samples 381147 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 313389 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 381147 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 313389 # Request fanout histogram
+system.membus.snoop_fanout::total 381147 # Request fanout histogram
system.membus.reqLayer0.occupancy 90494500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks)
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 50916 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total 205819701 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops 52269 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3285526 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 3.011103 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.104785 # Request fanout histogram
+system.toL2Bus.snoop_fanout::samples 3353284 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.021354 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.144561 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 3249046 98.89% 98.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 36480 1.11% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 3281678 97.86% 97.86% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 71606 2.14% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3285526 # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3353284 # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy 2359229000 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 201000 # Layer occupancy (ticks)
sim_ticks 5112152301500 # Number of ticks simulated
final_tick 5112152301500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1049184 # Simulator instruction rate (inst/s)
-host_op_rate 2147909 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26808985343 # Simulator tick rate (ticks/s)
-host_mem_usage 640900 # Number of bytes of host memory used
-host_seconds 190.69 # Real time elapsed on the host
+host_inst_rate 1219492 # Simulator instruction rate (inst/s)
+host_op_rate 2496566 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 31160731508 # Simulator tick rate (ticks/s)
+host_mem_usage 598628 # Number of bytes of host memory used
+host_seconds 164.06 # Real time elapsed on the host
sim_insts 200066731 # Number of instructions simulated
sim_ops 409580371 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.l2cache.ReadReq_hits::total 2064118 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 1538781 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 1538781 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 22 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 22 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 21 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 21 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 179771 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 179771 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6656 # number of demand (read+write) hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 13355 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 32163 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 45524 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1807 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1807 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data 1808 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 1808 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 134650 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 134650 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016847 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.024601 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.021579 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.987972 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::total 0.987972 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.988518 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::total 0.988518 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.428247 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.428247 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000150 # miss rate for demand accesses
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 320000 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 730240 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 279335801 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 48002 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4017264 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011855 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.108231 # Request fanout histogram
+system.cpu.toL2Bus.snoops 49698 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 17890240 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.002757 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.052432 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3969641 98.81% 98.81% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47623 1.19% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 17840921 99.72% 99.72% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 49319 0.28% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4017264 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 17890240 # Request fanout histogram
system.iobus.trans_dist::ReadReq 10012057 # Transaction distribution
system.iobus.trans_dist::ReadResp 10012057 # Transaction distribution
system.iobus.trans_dist::WriteReq 57724 # Transaction distribution
system.membus.trans_dist::Writeback 144777 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2545 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 2093 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2546 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 2094 # Transaction distribution
system.membus.trans_dist::ReadExReq 134369 # Transaction distribution
system.membus.trans_dist::ReadExResp 134364 # Transaction distribution
system.membus.trans_dist::MessageReq 1696 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::total 3392 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 20044316 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 7698244 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462529 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205089 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 462531 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 28205091 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141913 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141913 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 28350394 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 28350396 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6784 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6784 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 10028276 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6034560 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 49257977 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 374838 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::samples 14247815 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.000119 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.010910 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 374838 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 14246119 99.99% 99.99% # Request fanout histogram
+system.membus.snoop_fanout::2 1696 0.01% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 374838 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
+system.membus.snoop_fanout::total 14247815 # Request fanout histogram
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
sim_ticks 5184749789500 # Number of ticks simulated
final_tick 5184749789500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 858252 # Simulator instruction rate (inst/s)
-host_op_rate 1654417 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34581252938 # Simulator tick rate (ticks/s)
-host_mem_usage 653812 # Number of bytes of host memory used
-host_seconds 149.93 # Real time elapsed on the host
+host_inst_rate 812427 # Simulator instruction rate (inst/s)
+host_op_rate 1566083 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 32734861616 # Simulator tick rate (ticks/s)
+host_mem_usage 599680 # Number of bytes of host memory used
+host_seconds 158.39 # Real time elapsed on the host
sim_insts 128677191 # Number of instructions simulated
sim_ops 248045844 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bytesWrittenSys 11116160 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 95 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 26079 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 1618 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 1619 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9927 # Per bank write bursts
system.physmem.perBankRdBursts::1 9220 # Per bank write bursts
system.physmem.perBankRdBursts::2 9906 # Per bank write bursts
system.physmem.wrPerTurnAround::544-559 1 0.02% 99.96% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::656-671 2 0.04% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
-system.physmem.totQLat 1425327951 # Total ticks spent queuing
-system.physmem.totMemAccLat 4315621701 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1425306951 # Total ticks spent queuing
+system.physmem.totMemAccLat 4315600701 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 770745000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 9246.43 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 9246.29 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27996.43 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 27996.29 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.90 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.82 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.90 # Average system read bandwidth in MiByte/s
system.physmem_0.readEnergy 599352000 # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy 480232800 # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy 338642475600 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 133930608030 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 2993365407000 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 3467346236970 # Total energy per rank (pJ)
+system.physmem_0.actBackEnergy 133930593495 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 2993365419750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 3467346235185 # Total energy per rank (pJ)
system.physmem_0.averagePower 668.758961 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 4979642459610 # Time in different power states
+system.physmem_0.memoryStateTime::IDLE 4979642480610 # Time in different power states
system.physmem_0.memoryStateTime::REF 173130100000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 31977108390 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 31977087390 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem_1.actEnergy 218982960 # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy 119484750 # Energy for precharge commands per rank (pJ)
system.cpu.dcache.overall_misses::total 1634737 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 12835976218 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 12835976218 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149953096 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 12149953096 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 24985929314 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 24985929314 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 24985929314 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 24985929314 # number of overall miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 12149973597 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 12149973597 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 24985949815 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 24985949815 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 24985949815 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 24985949815 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 12921694 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28518 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 41460 # number of ReadReq MSHR misses
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-system.cpu.l2cache.UpgradeReq_mshr_misses::total 1357 # number of UpgradeReq MSHR misses
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system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113272 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 113272 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12937 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 141790 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154732 # number of overall MSHR misses
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+system.cpu.l2cache.WriteReq_mshr_uncacheable::total 13916 # number of WriteReq MSHR uncacheable
+system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 588728 # number of overall MSHR uncacheable misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 325250 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 887295749 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1984560718 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24688339 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24688339 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 24705840 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 24705840 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7236225029 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7236225029 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 325250 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 887295749 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9220785747 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 10108406746 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 325250 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 887295749 # number of overall MSHR miss cycles
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system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9220785747 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 10108406746 # number of overall MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86143480500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86143480500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2411090500 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016274 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021788 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019609 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.810633 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.810633 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.811231 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.811231 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361420 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361420 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001500 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087402 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063735 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65050 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 68585.896962 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 69589.757977 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.970019 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 18193.322771 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18193.322771 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69275.463507 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63883.616684 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63883.616684 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65050 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68585.896962 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65031.283920 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.482447 # average overall mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65328.346729 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 149863.747625 # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 149863.747625 # average ReadReq mshr uncacheable latency
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+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 173260.311871 # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 150416.781604 # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 150416.781604 # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.trans_dist::ReadReq 2695684 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2695162 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2193 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 313413 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 313413 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::MessageReq 1652 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1589955 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5966477 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 9396 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261888 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 656512 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total 255815469 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 54167 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4026617 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.011824 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.108093 # Request fanout histogram
+system.cpu.toL2Bus.snoops 55819 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4616997 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.010670 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.102742 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 3979007 98.82% 98.82% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47610 1.18% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4567735 98.93% 98.93% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 49262 1.07% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4026617 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4616997 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3834191500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 472500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1194868737 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3047835586 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 3047835587 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 7956750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.trans_dist::Writeback 126970 # Transaction distribution
system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2155 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1636 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2156 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1637 # Transaction distribution
system.membus.trans_dist::ReadExReq 112993 # Transaction distribution
system.membus.trans_dist::ReadExResp 112993 # Transaction distribution
system.membus.trans_dist::MessageReq 1652 # Transaction distribution
system.membus.pkt_count_system.apicbridge.master::total 3304 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 477136 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 700320 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392330 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569786 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 392332 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1569788 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 141387 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 141387 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1714477 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1714479 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.apicbridge.master::total 6608 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 244848 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 6005120 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total 22639869 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 1583 # Total snoops (count)
-system.membus.snoop_fanout::samples 331203 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::samples 921584 # Request fanout histogram
+system.membus.snoop_fanout::mean 1.001793 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.042301 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 331203 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 919932 99.82% 99.82% # Request fanout histogram
+system.membus.snoop_fanout::2 1652 0.18% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 331203 # Request fanout histogram
+system.membus.snoop_fanout::max_value 2 # Request fanout histogram
+system.membus.snoop_fanout::total 921584 # Request fanout histogram
system.membus.reqLayer0.occupancy 362661000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 527980000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 3304000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1034074968 # Layer occupancy (ticks)
+system.membus.reqLayer3.occupancy 1034075968 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.respLayer0.occupancy 1652000 # Layer occupancy (ticks)
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2159260415 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 2159262414 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
system.membus.respLayer4.occupancy 51084248 # Layer occupancy (ticks)
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
sim_ticks 200409271000 # Number of ticks simulated
final_tick 4321213476000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 10268281 # Simulator instruction rate (inst/s)
-host_op_rate 10268278 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3928851236 # Simulator tick rate (ticks/s)
-host_mem_usage 533084 # Number of bytes of host memory used
-host_seconds 51.01 # Real time elapsed on the host
+host_inst_rate 20752053 # Simulator instruction rate (inst/s)
+host_op_rate 20752044 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 7940152278 # Simulator tick rate (ticks/s)
+host_mem_usage 485568 # Number of bytes of host memory used
+host_seconds 25.24 # Real time elapsed on the host
sim_insts 523780905 # Number of instructions simulated
sim_ops 523780905 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.membus.pkt_size_drivesys.iobridge.master::total 57261614 # Cumulative packet size per connected master and slave (bytes)
drivesys.membus.pkt_size::total 175319714 # Cumulative packet size per connected master and slave (bytes)
drivesys.membus.snoops 0 # Total snoops (count)
-drivesys.membus.snoop_fanout::samples 27109094 # Request fanout histogram
-drivesys.membus.snoop_fanout::mean 0.790778 # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev 0.406753 # Request fanout histogram
+drivesys.membus.snoop_fanout::samples 27247410 # Request fanout histogram
+drivesys.membus.snoop_fanout::mean 0.786764 # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev 0.409593 # Request fanout histogram
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0 5671825 20.92% 20.92% # Request fanout histogram
-drivesys.membus.snoop_fanout::1 21437269 79.08% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0 5810141 21.32% 21.32% # Request fanout histogram
+drivesys.membus.snoop_fanout::1 21437269 78.68% 100.00% # Request fanout histogram
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-drivesys.membus.snoop_fanout::total 27109094 # Request fanout histogram
+drivesys.membus.snoop_fanout::total 27247410 # Request fanout histogram
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted
drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received
testsys.membus.pkt_size_testsys.iobridge.master::total 57261398 # Cumulative packet size per connected master and slave (bytes)
testsys.membus.pkt_size::total 183678150 # Cumulative packet size per connected master and slave (bytes)
testsys.membus.snoops 0 # Total snoops (count)
-testsys.membus.snoop_fanout::samples 28747524 # Request fanout histogram
-testsys.membus.snoop_fanout::mean 0.787786 # Request fanout histogram
-testsys.membus.snoop_fanout::stdev 0.408876 # Request fanout histogram
+testsys.membus.snoop_fanout::samples 28885173 # Request fanout histogram
+testsys.membus.snoop_fanout::mean 0.784032 # Request fanout histogram
+testsys.membus.snoop_fanout::stdev 0.411493 # Request fanout histogram
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0 6100637 21.22% 21.22% # Request fanout histogram
-testsys.membus.snoop_fanout::1 22646887 78.78% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0 6238286 21.60% 21.60% # Request fanout histogram
+testsys.membus.snoop_fanout::1 22646887 78.40% 100.00% # Request fanout histogram
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-testsys.membus.snoop_fanout::total 28747524 # Request fanout histogram
+testsys.membus.snoop_fanout::total 28885173 # Request fanout histogram
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted
testsys.tsunami.ethernet.rxBytes 798 # Bytes Received
sim_ticks 407341500 # Number of ticks simulated
final_tick 4321620817500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 5226750004 # Simulator instruction rate (inst/s)
-host_op_rate 5225740576 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4062718512 # Simulator tick rate (ticks/s)
-host_mem_usage 533084 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 10415397218 # Simulator instruction rate (inst/s)
+host_op_rate 10413013630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 8095289719 # Simulator tick rate (ticks/s)
+host_mem_usage 485568 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 523853183 # Number of instructions simulated
sim_ops 523853183 # Number of ops (including micro ops) simulated
drivesys.voltage_domain.voltage 1 # Voltage in Volts
drivesys.membus.pkt_size_drivesys.iobridge.master::total 116400 # Cumulative packet size per connected master and slave (bytes)
drivesys.membus.pkt_size::total 340576 # Cumulative packet size per connected master and slave (bytes)
drivesys.membus.snoops 0 # Total snoops (count)
-drivesys.membus.snoop_fanout::samples 51723 # Request fanout histogram
-drivesys.membus.snoop_fanout::mean 0.792723 # Request fanout histogram
-drivesys.membus.snoop_fanout::stdev 0.405360 # Request fanout histogram
+drivesys.membus.snoop_fanout::samples 52004 # Request fanout histogram
+drivesys.membus.snoop_fanout::mean 0.788439 # Request fanout histogram
+drivesys.membus.snoop_fanout::stdev 0.408419 # Request fanout histogram
drivesys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-drivesys.membus.snoop_fanout::0 10721 20.73% 20.73% # Request fanout histogram
-drivesys.membus.snoop_fanout::1 41002 79.27% 100.00% # Request fanout histogram
+drivesys.membus.snoop_fanout::0 11002 21.16% 21.16% # Request fanout histogram
+drivesys.membus.snoop_fanout::1 41002 78.84% 100.00% # Request fanout histogram
drivesys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
drivesys.membus.snoop_fanout::min_value 0 # Request fanout histogram
drivesys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-drivesys.membus.snoop_fanout::total 51723 # Request fanout histogram
+drivesys.membus.snoop_fanout::total 52004 # Request fanout histogram
drivesys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
drivesys.tsunami.ethernet.descDMAReads 4850 # Number of descriptors the device read w/ DMA
drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
testsys.membus.pkt_size_testsys.iobridge.master::total 116376 # Cumulative packet size per connected master and slave (bytes)
testsys.membus.pkt_size::total 340448 # Cumulative packet size per connected master and slave (bytes)
testsys.membus.snoops 0 # Total snoops (count)
-testsys.membus.snoop_fanout::samples 51694 # Request fanout histogram
-testsys.membus.snoop_fanout::mean 0.792645 # Request fanout histogram
-testsys.membus.snoop_fanout::stdev 0.405416 # Request fanout histogram
+testsys.membus.snoop_fanout::samples 51975 # Request fanout histogram
+testsys.membus.snoop_fanout::mean 0.788360 # Request fanout histogram
+testsys.membus.snoop_fanout::stdev 0.408475 # Request fanout histogram
testsys.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-testsys.membus.snoop_fanout::0 10719 20.74% 20.74% # Request fanout histogram
-testsys.membus.snoop_fanout::1 40975 79.26% 100.00% # Request fanout histogram
+testsys.membus.snoop_fanout::0 11000 21.16% 21.16% # Request fanout histogram
+testsys.membus.snoop_fanout::1 40975 78.84% 100.00% # Request fanout histogram
testsys.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
testsys.membus.snoop_fanout::min_value 0 # Request fanout histogram
testsys.membus.snoop_fanout::max_value 1 # Request fanout histogram
-testsys.membus.snoop_fanout::total 51694 # Request fanout histogram
+testsys.membus.snoop_fanout::total 51975 # Request fanout histogram
testsys.tsunami.ethernet.clk_domain.clock 2000 # Clock period in ticks
testsys.tsunami.ethernet.descDMAReads 4849 # Number of descriptors the device read w/ DMA
testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.cpu.toL2Bus.pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 468 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 468 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%)
sim_ticks 17398000 # Number of ticks simulated
final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 32773 # Simulator instruction rate (inst/s)
-host_op_rate 38377 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 124135140 # Simulator tick rate (ticks/s)
-host_mem_usage 303432 # Number of bytes of host memory used
-host_seconds 0.14 # Real time elapsed on the host
+host_inst_rate 57922 # Simulator instruction rate (inst/s)
+host_op_rate 67825 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 219380871 # Simulator tick rate (ticks/s)
+host_mem_usage 310080 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 440 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 64 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1.127237 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 439 87.28% 87.28% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 64 12.72% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 88081 # Simulator instruction rate (inst/s)
-host_op_rate 103121 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 51657705 # Simulator tick rate (ticks/s)
-host_mem_usage 292672 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 803078 # Simulator instruction rate (inst/s)
+host_op_rate 938405 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 469266934 # Simulator tick rate (ticks/s)
+host_mem_usage 299548 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
-system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
+system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 6532 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 2695000 # Number of ticks simulated
final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99386 # Simulator instruction rate (inst/s)
-host_op_rate 116351 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 58281162 # Simulator tick rate (ticks/s)
-host_mem_usage 291652 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 829930 # Simulator instruction rate (inst/s)
+host_op_rate 969708 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 484799424 # Simulator tick rate (ticks/s)
+host_mem_usage 298800 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 4592 # Number of instructions simulated
sim_ops 5378 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 6532 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.704991 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram
-system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1927 29.50% 29.50% # Request fanout histogram
+system.membus.snoop_fanout::1 4605 70.50% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 6532 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
system.cpu.toL2Bus.pkt_size::total 26688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 418 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 418 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 418 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 418 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 209000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
sim_ticks 5615000 # Number of ticks simulated
final_tick 5615000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 365210 # Simulator instruction rate (inst/s)
-host_op_rate 661016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 380445830 # Simulator tick rate (ticks/s)
-host_mem_usage 292780 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 96804 # Simulator instruction rate (inst/s)
+host_op_rate 175298 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 100934348 # Simulator tick rate (ticks/s)
+host_mem_usage 242164 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 9779519145 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2525022262 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 12304541407 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 7917 # Transaction distribution
-system.membus.trans_dist::ReadResp 7917 # Transaction distribution
-system.membus.trans_dist::WriteReq 935 # Transaction distribution
-system.membus.trans_dist::WriteResp 935 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 8852 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.775418 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 1988 22.46% 22.46% # Request fanout histogram
-system.membus.snoop_fanout::3 6864 77.54% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 8852 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 11 # Number of system calls
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 9748 # Class of executed instruction
+system.membus.trans_dist::ReadReq 7917 # Transaction distribution
+system.membus.trans_dist::ReadResp 7917 # Transaction distribution
+system.membus.trans_dist::WriteReq 935 # Transaction distribution
+system.membus.trans_dist::WriteResp 935 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 13728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 13728 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3976 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 3976 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 17704 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 54912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 54912 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 14178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 14178 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 69090 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 8852 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.775418 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.417330 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 1988 22.46% 22.46% # Request fanout histogram
+system.membus.snoop_fanout::1 6864 77.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 8852 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 28358500 # Number of ticks simulated
final_tick 28358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 312703 # Simulator instruction rate (inst/s)
-host_op_rate 566020 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1645401799 # Simulator tick rate (ticks/s)
-host_mem_usage 307640 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 97635 # Simulator instruction rate (inst/s)
+host_op_rate 176805 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 514168344 # Simulator tick rate (ticks/s)
+host_mem_usage 251928 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
sim_insts 5381 # Number of instructions simulated
sim_ops 9748 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 23168 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 362 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 362 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 362 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 362 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 181000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%)
sim_ticks 54141000500 # Number of ticks simulated
final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1362402 # Simulator instruction rate (inst/s)
-host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 814125846 # Simulator tick rate (ticks/s)
-host_mem_usage 428768 # Number of bytes of host memory used
-host_seconds 66.50 # Real time elapsed on the host
+host_inst_rate 1892320 # Simulator instruction rate (inst/s)
+host_op_rate 1901744 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1130787212 # Simulator tick rate (ticks/s)
+host_mem_usage 435148 # Number of bytes of host memory used
+host_seconds 47.88 # Real time elapsed on the host
sim_insts 90602408 # Number of instructions simulated
sim_ops 91053639 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 135031171 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.798562 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram
-system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 27200400 20.14% 20.14% # Request fanout histogram
+system.membus.snoop_fanout::1 107830771 79.86% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 135031171 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 120942784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 1889731 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 1889731 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 1889731 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 1889731 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 1887199500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%)
sim_ticks 168950040000 # Number of ticks simulated
final_tick 168950040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1180838 # Simulator instruction rate (inst/s)
-host_op_rate 2079266 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1262766288 # Simulator tick rate (ticks/s)
-host_mem_usage 436624 # Number of bytes of host memory used
-host_seconds 133.79 # Real time elapsed on the host
+host_inst_rate 1204419 # Simulator instruction rate (inst/s)
+host_op_rate 2120788 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1287982979 # Simulator tick rate (ticks/s)
+host_mem_usage 383444 # Number of bytes of host memory used
+host_seconds 131.17 # Real time elapsed on the host
sim_insts 157988548 # Number of instructions simulated
sim_ops 278192465 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 10308191179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 5684633931 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 15992825110 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
-system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
-system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
-system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.640442 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 122219199 35.96% 35.96% # Request fanout histogram
-system.membus.snoop_fanout::3 217696164 64.04% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 339915363 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 278192465 # Class of executed instruction
+system.membus.trans_dist::ReadReq 308475611 # Transaction distribution
+system.membus.trans_dist::ReadResp 308475611 # Transaction distribution
+system.membus.trans_dist::WriteReq 31439752 # Transaction distribution
+system.membus.trans_dist::WriteResp 31439752 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 435392328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 435392328 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 244438398 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 244438398 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679830726 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1741569312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1741569312 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 960419130 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 960419130 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 2701988442 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 339915363 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.640442 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.479871 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 122219199 35.96% 35.96% # Request fanout histogram
+system.membus.snoop_fanout::1 217696164 64.04% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 339915363 # Request fanout histogram
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000730 # Number of seconds simulated
-sim_ticks 729906500 # Number of ticks simulated
-final_tick 729906500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 0.000790 # Number of seconds simulated
+sim_ticks 789792500 # Number of ticks simulated
+final_tick 789792500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 158517498 # Simulator tick rate (ticks/s)
-host_mem_usage 277860 # Number of bytes of host memory used
-host_seconds 4.60 # Real time elapsed on the host
+host_tick_rate 129975147 # Simulator tick rate (ticks/s)
+host_mem_usage 221936 # Number of bytes of host memory used
+host_seconds 6.08 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 76606 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 79713 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 76745 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 78087 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 75189 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 77277 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 77630 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 79795 # Number of bytes read from this memory
-system.physmem.bytes_read::total 621042 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 386688 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5350 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5335 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5543 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5464 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5476 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5444 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5451 # Number of bytes written to this memory
-system.physmem.bytes_written::total 430089 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 10897 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 11106 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10910 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 10803 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10929 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10812 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 10850 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10810 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87117 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6042 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5350 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5335 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5543 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5464 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5476 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5444 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5451 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 49443 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 104953169 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 109209878 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 105143604 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 106982196 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 103011824 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 105872464 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 106356088 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 109322221 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 850851445 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 529777444 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 7329706 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 7309155 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 7313265 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 7594123 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 7485890 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 7502331 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 7458490 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 7468080 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 589238485 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 529777444 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 112282875 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 116519034 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 112456869 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 114576319 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 110497714 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 113374795 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 113814578 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 116790301 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1440089929 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 78179 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 78681 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 79146 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 76465 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 76157 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 75918 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 79229 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 81414 # Number of bytes read from this memory
+system.physmem.bytes_read::total 625189 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 393152 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5414 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5436 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5494 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5519 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5358 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5458 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5447 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5462 # Number of bytes written to this memory
+system.physmem.bytes_written::total 436740 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11021 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11082 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10980 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10945 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11015 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 10965 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10874 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10980 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87862 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6143 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5414 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5436 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5494 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5519 # Number of write requests responded to by this memory
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system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 33269.805355 # average overall mshr miss latency
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+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 189106.368918 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.num_reads 100000 # number of read accesses completed
-system.cpu1.num_writes 54938 # number of write accesses completed
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system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 33234.339403 # average overall mshr miss latency
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+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78009.472927 # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 393823.767194 # average WriteReq mshr uncacheable latency
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+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 189182.319394 # average overall mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 189182.319394 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 55356 # number of write accesses completed
-system.cpu2.l1c.tags.replacements 22413 # number of replacements
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-system.cpu2.l1c.tags.sampled_refs 22815 # Sample count of references to valid blocks.
-system.cpu2.l1c.tags.avg_refs 0.589437 # Average number of references to valid blocks.
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system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.l1c.overall_avg_miss_latency::cpu2 32089.900131 # average overall miss latency
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system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu2.l1c.fast_writes 0 # number of fast writes performed
system.cpu2.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 33304.211199 # average overall mshr miss latency
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+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 188618.643326 # average overall mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 188618.643326 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 55322 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22357 # number of replacements
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-system.cpu3.l1c.tags.sampled_refs 22743 # Sample count of references to valid blocks.
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system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu3.l1c.fast_writes 0 # number of fast writes performed
system.cpu3.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 33302.973807 # average overall mshr miss latency
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+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 188662.312613 # average overall mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 188662.312613 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 55538 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22215 # number of replacements
-system.cpu4.l1c.tags.tagsinuse 391.788113 # Cycle average of tags in use
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-system.cpu4.l1c.tags.sampled_refs 22618 # Sample count of references to valid blocks.
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu4.l1c.fast_writes 0 # number of fast writes performed
system.cpu4.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78189.521739 # average ReadReq mshr uncacheable latency
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+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 188611.039369 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu5.num_writes 55102 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22389 # number of replacements
-system.cpu5.l1c.tags.tagsinuse 394.368473 # Cycle average of tags in use
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-system.cpu5.l1c.tags.sampled_refs 22785 # Sample count of references to valid blocks.
-system.cpu5.l1c.tags.avg_refs 0.597411 # Average number of references to valid blocks.
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu5.l1c.overall_avg_miss_latency::total 32179.767390 # average overall miss latency
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 40210.004405 # average WriteReq mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 33218.470757 # average overall mshr miss latency
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+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 189674.774523 # average overall mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 189674.774523 # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu6.num_writes 55520 # number of write accesses completed
-system.cpu6.l1c.tags.replacements 22403 # number of replacements
-system.cpu6.l1c.tags.tagsinuse 393.263413 # Cycle average of tags in use
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-system.cpu6.l1c.tags.avg_refs 0.595989 # Average number of references to valid blocks.
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 33315.773790 # average overall mshr miss latency
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+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 190652.015224 # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 190652.015224 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 55051 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22600 # number of replacements
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-system.cpu7.l1c.tags.sampled_refs 22986 # Sample count of references to valid blocks.
-system.cpu7.l1c.tags.avg_refs 0.582093 # Average number of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
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+system.cpu7.l1c.overall_mshr_miss_rate::total 0.860603 # mshr miss rate for overall accesses
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+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 28669.614488 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 40283.587541 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 40283.587541 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 33264.433289 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 33264.433289 # average overall mshr miss latency
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+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total 78083.642162 # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 390763.704483 # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total 390763.704483 # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 189572.944738 # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 189572.944738 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 12974 # number of replacements
-system.l2c.tags.tagsinuse 782.339791 # Cycle average of tags in use
-system.l2c.tags.total_refs 149980 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 13746 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 10.910810 # Average number of references to valid blocks.
+system.l2c.tags.replacements 12865 # number of replacements
+system.l2c.tags.tagsinuse 778.482244 # Cycle average of tags in use
+system.l2c.tags.total_refs 150454 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 13664 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 11.010978 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 728.962494 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0 6.892190 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.186949 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 6.375204 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 6.806314 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 6.399875 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 6.389081 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 6.432209 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.895475 # Average occupied blocks per requestor
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-system.l2c.tags.occ_task_id_blocks::1024 772 # Occupied blocks per task id
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-system.l2c.ReadReq_hits::cpu7 10669 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 85605 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 75955 # number of Writeback hits
-system.l2c.Writeback_hits::total 75955 # number of Writeback hits
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-system.l2c.UpgradeReq_hits::cpu2 335 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3 336 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu4 340 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 357 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 325 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu7 325 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 2692 # number of UpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu4 1880 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu5 1895 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu6 1918 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu7 1918 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu6 12571 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu4 12609 # number of overall hits
-system.l2c.overall_hits::cpu5 12579 # number of overall hits
-system.l2c.overall_hits::cpu6 12571 # number of overall hits
-system.l2c.overall_hits::cpu7 12587 # number of overall hits
-system.l2c.overall_hits::total 100988 # number of overall hits
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-system.l2c.ReadReq_misses::cpu6 670 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu7 712 # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu3 1923 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 1955 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 1959 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1992 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1968 # number of UpgradeReq misses
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-system.l2c.ReadExReq_misses::cpu3 4368 # number of ReadExReq misses
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-system.l2c.ReadExReq_misses::cpu5 4389 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6 4443 # number of ReadExReq misses
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-system.l2c.demand_misses::cpu4 5102 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu5 5073 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu6 5113 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu4 5102 # number of overall misses
-system.l2c.overall_misses::cpu5 5073 # number of overall misses
-system.l2c.overall_misses::cpu6 5113 # number of overall misses
-system.l2c.overall_misses::cpu7 5101 # number of overall misses
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-system.l2c.Writeback_accesses::total 75955 # number of Writeback accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::cpu5 2316 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_accesses::total 18292 # number of UpgradeReq accesses(hits+misses)
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.851316 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.848485 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.851262 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.851852 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.845855 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.859732 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.858264 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.852832 # miss rate for UpgradeReq accesses
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.ReadReq_mshr_miss_rate::cpu0 0.055477 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1 0.059623 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2 0.060499 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3 0.057530 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4 0.056918 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5 0.058876 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6 0.059168 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7 0.061338 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.058679 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.886593 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.877489 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.886275 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.885033 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.873803 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.875055 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.875445 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.878841 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.879829 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.724830 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.717361 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.725925 # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for demand accesses
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+system.l2c.demand_mshr_miss_rate::total 0.297002 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0 0.295843 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu4 0.293910 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5 0.300073 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total 0.297002 # mshr miss rate for overall accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 49560.205882 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 42023.052058 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 42024.665022 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41973.691740 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41943.872059 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 42061.253984 # average UpgradeReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 42532.000221 # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 42572.928914 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 42752.761252 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 42518.913352 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 42577.411200 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 42711.187992 # average ReadExReq mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu4 43490.076747 # average overall mshr miss latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 42224.986139 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 42205.960835 # average ReadReq mshr uncacheable latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3 42247.656067 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 42187.784813 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 42208.018220 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 42198.566292 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 42191.319002 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 42209.276063 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 43795.063539 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 43742.269132 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 43994.444121 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 43681.279217 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 44035.736842 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 44163.151337 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 43823.506608 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 43951.753387 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 43898.066118 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0 42778.037476 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1 42746.677695 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 42846.831666 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 42760.600389 # average overall mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::total 42808.113328 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.snoop_filter.tot_requests 123330 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 121282 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.tot_requests 252480 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 249408 # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.trans_dist::ReadReq 84079 # Transaction distribution
-system.membus.trans_dist::ReadResp 84076 # Transaction distribution
-system.membus.trans_dist::WriteReq 43401 # Transaction distribution
-system.membus.trans_dist::WriteResp 43399 # Transaction distribution
-system.membus.trans_dist::Writeback 6042 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 58662 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 47800 # Transaction distribution
-system.membus.trans_dist::ReadExReq 50251 # Transaction distribution
-system.membus.trans_dist::ReadExResp 3038 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 420748 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 420748 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1051128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1051128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 58073 # Total snoops (count)
-system.membus.snoop_fanout::samples 123330 # Request fanout histogram
+system.membus.trans_dist::ReadReq 84654 # Transaction distribution
+system.membus.trans_dist::ReadResp 84652 # Transaction distribution
+system.membus.trans_dist::WriteReq 43588 # Transaction distribution
+system.membus.trans_dist::WriteResp 43585 # Transaction distribution
+system.membus.trans_dist::Writeback 6143 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60492 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 49595 # Transaction distribution
+system.membus.trans_dist::ReadExReq 50638 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3207 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 426554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 426554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1061863 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1061863 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 58325 # Total snoops (count)
+system.membus.snoop_fanout::samples 252480 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123330 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 252480 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123330 # Request fanout histogram
-system.membus.reqLayer0.occupancy 349185814 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 47.8 # Layer utilization (%)
-system.membus.respLayer0.occupancy 311191349 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 42.6 # Layer utilization (%)
-system.toL2Bus.snoop_filter.tot_requests 561297 # Total number of requests made to the snoop filter.
-system.toL2Bus.snoop_filter.hit_single_requests 261699 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.toL2Bus.snoop_filter.hit_multi_requests 297550 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_fanout::total 252480 # Request fanout histogram
+system.membus.reqLayer0.occupancy 472884580 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 59.9 # Layer utilization (%)
+system.membus.respLayer0.occupancy 313892142 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 39.7 # Layer utilization (%)
+system.toL2Bus.snoop_filter.tot_requests 684630 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 383351 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 298207 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.toL2Bus.trans_dist::ReadReq 370588 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370576 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 3 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43402 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43399 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 75955 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29152 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29150 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 162499 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 162497 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120510 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120652 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120226 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120519 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120569 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120393 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120447 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120346 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 963662 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1766434 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757944 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1752931 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1758190 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1756878 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1755329 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1752897 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1753790 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14054393 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 323559 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 561297 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.683086 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 1.176196 # Request fanout histogram
+system.toL2Bus.trans_dist::ReadReq 371695 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 371689 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 43589 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 43585 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 75954 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29169 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29167 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 162397 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 162391 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120614 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120783 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120664 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120646 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120853 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120726 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120516 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120736 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 965538 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1756616 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1750933 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1748576 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1754368 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1762730 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756512 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1757509 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1755676 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14042920 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 324098 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 684630 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.384232 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.250303 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 53942 9.61% 9.61% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 251180 44.75% 54.36% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 141382 25.19% 79.55% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 68926 12.28% 91.83% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 30158 5.37% 97.20% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 11557 2.06% 99.26% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 3492 0.62% 99.88% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 660 0.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 176832 25.83% 25.83% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 250927 36.65% 62.48% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 141295 20.64% 83.12% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 69195 10.11% 93.23% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 30377 4.44% 97.66% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11672 1.70% 99.37% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3607 0.53% 99.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 725 0.11% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 561297 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 720580520 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 98.7 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 100512947 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 100775889 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 100644932 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 100575951 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 100528413 # Layer occupancy (ticks)
-system.toL2Bus.respLayer4.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 100450921 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 100623449 # Layer occupancy (ticks)
-system.toL2Bus.respLayer6.utilization 13.8 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 100655480 # Layer occupancy (ticks)
-system.toL2Bus.respLayer7.utilization 13.8 # Layer utilization (%)
+system.toL2Bus.snoop_fanout::total 684630 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 782327755 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 99.1 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 100591456 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 12.7 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 100721944 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 100768962 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 100555978 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 12.7 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 100847968 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 100723976 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 100740497 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 12.8 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 100846524 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 12.8 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 0.000473 # Number of seconds simulated
-sim_ticks 473250000 # Number of ticks simulated
-final_tick 473250000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 473398500 # Number of ticks simulated
+final_tick 473398500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 101630905 # Simulator tick rate (ticks/s)
-host_mem_usage 277340 # Number of bytes of host memory used
-host_seconds 4.66 # Real time elapsed on the host
+host_tick_rate 74773462 # Simulator tick rate (ticks/s)
+host_mem_usage 221944 # Number of bytes of host memory used
+host_seconds 6.33 # Real time elapsed on the host
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0 80424 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1 83171 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2 80813 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3 86214 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu4 79490 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu5 82665 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu6 85333 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu7 80902 # Number of bytes read from this memory
-system.physmem.bytes_read::total 659012 # Number of bytes read from this memory
-system.physmem.bytes_written::writebacks 419392 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0 5460 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1 5448 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu2 5355 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu3 5405 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu4 5451 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu5 5481 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu6 5462 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu7 5450 # Number of bytes written to this memory
-system.physmem.bytes_written::total 462904 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0 11061 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1 10973 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2 10946 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3 11055 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu4 10883 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu5 10908 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu6 11056 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu7 10909 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 87791 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 6553 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0 5460 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1 5448 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu2 5355 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu3 5405 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu4 5451 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu5 5481 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu6 5462 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu7 5450 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 50065 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0 169939778 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1 175744321 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2 170761754 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3 182174326 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu4 167966191 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu5 174675119 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu6 180312731 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu7 170949815 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1392524036 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 886195457 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0 11537242 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1 11511886 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu2 11315372 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu3 11421025 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu4 11518225 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu5 11581616 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu6 11541469 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu7 11516112 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 978138405 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 886195457 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0 181477021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1 187256207 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2 182077126 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3 193595351 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu4 179484416 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu5 186256735 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu6 191854200 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu7 182465927 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2370662441 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bytes_read::cpu0 85610 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 86349 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 81279 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 82686 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 83314 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 81031 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 83113 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 86498 # Number of bytes read from this memory
+system.physmem.bytes_read::total 669880 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 430080 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5517 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5460 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5549 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5366 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5369 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5497 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5427 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 473601 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11018 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11064 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 10845 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10992 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 10927 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11038 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 10915 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 10898 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 87697 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6720 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5517 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5460 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5549 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5366 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5369 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5497 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5427 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5336 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 50241 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 180841300 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 182402352 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 171692559 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 174664685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 175991263 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 171168688 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 175566674 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 182717098 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1415044619 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 908494640 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 11654029 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 11533623 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 11721626 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 11335059 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 11341396 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 11611782 # Write bandwidth from this memory (bytes/s)
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+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total 104818.597760 # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.num_writes 54743 # number of write accesses completed
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system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total 103970.909470 # average overall mshr uncacheable latency
system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu2.num_writes 54617 # number of write accesses completed
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system.cpu2.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total 104837.549192 # average overall mshr uncacheable latency
system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu3.num_writes 55095 # number of write accesses completed
-system.cpu3.l1c.tags.replacements 22209 # number of replacements
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system.cpu3.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total 105246.778464 # average overall mshr uncacheable latency
system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu4.num_writes 55186 # number of write accesses completed
-system.cpu4.l1c.tags.replacements 22162 # number of replacements
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system.cpu4.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total 105312.635661 # average overall mshr uncacheable latency
system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu5.num_writes 54966 # number of write accesses completed
-system.cpu5.l1c.tags.replacements 22337 # number of replacements
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-system.cpu5.l1c.tags.sampled_refs 22755 # Sample count of references to valid blocks.
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system.cpu5.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total 104733.178099 # average overall mshr uncacheable latency
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-system.cpu6.num_writes 54752 # number of write accesses completed
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system.cpu6.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total 105635.765809 # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu7.num_writes 54915 # number of write accesses completed
-system.cpu7.l1c.tags.replacements 22352 # number of replacements
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-system.cpu7.l1c.tags.sampled_refs 22758 # Sample count of references to valid blocks.
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system.cpu7.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total 104740.650173 # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.l2c.tags.tagsinuse 783.697862 # Cycle average of tags in use
-system.l2c.tags.total_refs 151322 # Total number of references to valid blocks.
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+system.l2c.tags.replacements 14031 # number of replacements
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+system.l2c.tags.avg_refs 10.137186 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.l2c.tags.occ_blocks::cpu0 7.094586 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1 7.546674 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2 7.606935 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3 7.397120 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu4 7.288170 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu5 7.917650 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu6 7.470007 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu7 6.974735 # Average occupied blocks per requestor
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-system.l2c.UpgradeReq_hits::cpu4 376 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu5 343 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu6 361 # number of UpgradeReq hits
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-system.l2c.UpgradeReq_misses::cpu3 1935 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu4 2000 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu5 2012 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu6 1921 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu7 1987 # number of UpgradeReq misses
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-system.l2c.ReadExReq_misses::cpu5 4506 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu6 4417 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu7 4371 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 35170 # number of ReadExReq misses
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-system.l2c.demand_misses::cpu5 5265 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu6 5147 # number of overall misses
-system.l2c.overall_misses::cpu7 5089 # number of overall misses
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-system.l2c.UpgradeReq_miss_rate::cpu1 0.837288 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2 0.836332 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3 0.840573 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu4 0.841751 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu5 0.854352 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu6 0.841805 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu7 0.855728 # miss rate for UpgradeReq accesses
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system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.883579 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.873946 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.874009 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.888603 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.878654 # mshr miss rate for UpgradeReq accesses
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 84510 # Transaction distribution
-system.membus.trans_dist::ReadResp 84504 # Transaction distribution
-system.membus.trans_dist::WriteReq 43512 # Transaction distribution
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-system.membus.trans_dist::Writeback 6553 # Transaction distribution
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-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1121847 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1121847 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 56880 # Total snoops (count)
-system.membus.snoop_fanout::samples 123632 # Request fanout histogram
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+system.membus.trans_dist::ReadResp 84365 # Transaction distribution
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+system.membus.trans_dist::Writeback 6720 # Transaction distribution
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+system.membus.trans_dist::ReadExResp 3325 # Transaction distribution
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+system.membus.pkt_count::total 425122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 1143411 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1143411 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 57048 # Total snoops (count)
+system.membus.snoop_fanout::samples 253034 # Request fanout histogram
system.membus.snoop_fanout::mean 0 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 123632 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 253034 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 123632 # Request fanout histogram
-system.membus.reqLayer0.occupancy 285799779 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 60.4 # Layer utilization (%)
-system.membus.respLayer0.occupancy 306149550 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 64.7 # Layer utilization (%)
-system.toL2Bus.trans_dist::ReadReq 370575 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 370557 # Transaction distribution
-system.toL2Bus.trans_dist::ReadRespWithInvalidate 7 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 43514 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 43509 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 76857 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 29562 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 29559 # Transaction distribution
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-system.toL2Bus.trans_dist::ReadExResp 161024 # Transaction distribution
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-system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120575 # Packet count per connected master and slave (bytes)
+system.membus.snoop_fanout::total 253034 # Request fanout histogram
+system.membus.reqLayer0.occupancy 288296633 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 60.9 # Layer utilization (%)
+system.membus.respLayer0.occupancy 308136269 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 65.1 # Layer utilization (%)
+system.toL2Bus.trans_dist::ReadReq 369990 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 369967 # Transaction distribution
+system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 # Transaction distribution
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+system.toL2Bus.trans_dist::WriteResp 43518 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 76544 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 29606 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 29605 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 161002 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 160999 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 120638 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 120231 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 120590 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120769 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120586 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120766 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120584 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120839 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 965293 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1758906 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1769834 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1777815 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1771618 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1766732 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1791122 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1765164 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1788112 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 14189303 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 320901 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 563826 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 120464 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 120699 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 120288 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 120457 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 120419 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 963786 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1770551 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1757664 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1763883 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1765044 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1785450 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1756799 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1766043 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1776312 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 14141746 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 320975 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 687560 # Request fanout histogram
system.toL2Bus.snoop_fanout::mean 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::7 563826 100.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 687560 100.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 7 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 563826 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 445759226 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 94.2 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 101149991 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 687560 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 445191055 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 94.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 101323906 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 101191512 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 101359906 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 101013875 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 101243878 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 101648274 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 21.5 # Layer utilization (%)
-system.toL2Bus.respLayer4.occupancy 101307289 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 101066643 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 101367492 # Layer occupancy (ticks)
system.toL2Bus.respLayer4.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer5.occupancy 101134998 # Layer occupancy (ticks)
-system.toL2Bus.respLayer5.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer6.occupancy 101213033 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.occupancy 100955896 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 21.3 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 101182766 # Layer occupancy (ticks)
system.toL2Bus.respLayer6.utilization 21.4 # Layer utilization (%)
-system.toL2Bus.respLayer7.occupancy 101242964 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.occupancy 101290842 # Layer occupancy (ticks)
system.toL2Bus.respLayer7.utilization 21.4 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 48960011500 # Number of ticks simulated
final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1111911 # Simulator instruction rate (inst/s)
-host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 767686935 # Simulator tick rate (ticks/s)
-host_mem_usage 303468 # Number of bytes of host memory used
-host_seconds 63.78 # Real time elapsed on the host
+host_inst_rate 1547474 # Simulator instruction rate (inst/s)
+host_op_rate 1979004 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1068409192 # Simulator tick rate (ticks/s)
+host_mem_usage 311136 # Number of bytes of host memory used
+host_seconds 45.83 # Real time elapsed on the host
sim_insts 70913182 # Number of instructions simulated
sim_ops 90688137 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 120930619 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.646198 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram
-system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 42785550 35.38% 35.38% # Request fanout histogram
+system.membus.snoop_fanout::1 78145069 64.62% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 120930619 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 19657280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 307145 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 307145 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 307145 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 307145 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 281811500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
sim_ticks 99596491500 # Number of ticks simulated
final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1304038 # Simulator instruction rate (inst/s)
-host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 753711187 # Simulator tick rate (ticks/s)
-host_mem_usage 298984 # Number of bytes of host memory used
-host_seconds 132.14 # Real time elapsed on the host
+host_inst_rate 1968226 # Simulator instruction rate (inst/s)
+host_op_rate 2074827 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1137600357 # Simulator tick rate (ticks/s)
+host_mem_usage 306644 # Number of bytes of host memory used
+host_seconds 87.55 # Real time elapsed on the host
sim_insts 172317410 # Number of instructions simulated
sim_ops 181650342 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 0 # Total snoops (count)
system.membus.snoop_fanout::samples 230024467 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.825391 # Request fanout histogram
system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram
-system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::0 40164415 17.46% 17.46% # Request fanout histogram
+system.membus.snoop_fanout::1 189860052 82.54% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
system.membus.snoop_fanout::total 230024467 # Request fanout histogram
---------- End Simulation Statistics ----------
system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 4856 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4856 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 4856 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 4856 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 2444000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
sim_ticks 131393279000 # Number of ticks simulated
final_tick 131393279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1264426 # Simulator instruction rate (inst/s)
-host_op_rate 2119294 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1257935779 # Simulator tick rate (ticks/s)
-host_mem_usage 324376 # Number of bytes of host memory used
-host_seconds 104.45 # Real time elapsed on the host
+host_inst_rate 851639 # Simulator instruction rate (inst/s)
+host_op_rate 1427424 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 847267215 # Simulator tick rate (ticks/s)
+host_mem_usage 272248 # Number of bytes of host memory used
+host_seconds 155.08 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.physmem.bw_total::cpu.inst 10563363260 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3122274945 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 13685638205 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
-system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
-system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
-system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
-system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
-system.membus.snoop_fanout::mean 2.692062 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::2 77197736 30.79% 30.79% # Request fanout histogram
-system.membus.snoop_fanout::3 173494367 69.21% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 2 # Request fanout histogram
-system.membus.snoop_fanout::max_value 3 # Request fanout histogram
-system.membus.snoop_fanout::total 250692103 # Request fanout histogram
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::total 221363385 # Class of executed instruction
+system.membus.trans_dist::ReadReq 230176372 # Transaction distribution
+system.membus.trans_dist::ReadResp 230176372 # Transaction distribution
+system.membus.trans_dist::WriteReq 20515731 # Transaction distribution
+system.membus.trans_dist::WriteResp 20515731 # Transaction distribution
+system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.icache_port::total 346988734 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.dcache_port::total 154395472 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 501384206 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.icache_port::total 1387954936 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.dcache_port::total 410245943 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 1798200879 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 250692103 # Request fanout histogram
+system.membus.snoop_fanout::mean 0.692062 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0.461641 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 77197736 30.79% 30.79% # Request fanout histogram
+system.membus.snoop_fanout::1 173494367 69.21% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 250692103 # Request fanout histogram
---------- End Simulation Statistics ----------
sim_ticks 250953957500 # Number of ticks simulated
final_tick 250953957500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 722726 # Simulator instruction rate (inst/s)
-host_op_rate 1211354 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1373280924 # Simulator tick rate (ticks/s)
-host_mem_usage 338728 # Number of bytes of host memory used
-host_seconds 182.74 # Real time elapsed on the host
+host_inst_rate 582427 # Simulator instruction rate (inst/s)
+host_op_rate 976201 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1106694320 # Simulator tick rate (ticks/s)
+host_mem_usage 282016 # Number of bytes of host memory used
+host_seconds 226.76 # Real time elapsed on the host
sim_insts 132071193 # Number of instructions simulated
sim_ops 221363385 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.cpu.toL2Bus.pkt_size::total 422784 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples 6606 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 6606 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 6606 100.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total 6606 # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy 3310000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
projects / gem5.git / commitdiff