add err wishbone feature to Tercel

diff --git a/src/ls2.py b/src/ls2.py
index 315224569c166ebb26ad3a83659140ece47fc00f..92c990b87abaeb15d4abd826e6c79eb73b5e8e78 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -411,7 +411,7 @@ class DDR3SoC(SoC, Elaboratable):
             # The main SPI Flash (SPI 1) should be set to at
             # least 28 bits (256MB) to allow the use of large 4BA devices.
             self.spi0 = Tercel(data_width=32, spi_region_addr_width=24,
-                               features={'stall'},
+                               features={'stall', 'err'},
                                clk_freq=clk_freq,
                                pins=spi_0_pins,
                                lattice_ecp5_usrmclk=spi0_is_lattice_ecp5_clk)