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diff --git a/180nm_Oct2020/interfaces.mdwn b/180nm_Oct2020/interfaces.mdwn
index 685e3bdeb770ee55934b5e4f4348090f77ec087c..d8747a37a6ce7099a65a6e5c0c6758c4c0125c2d 100644 (file)
--- a/180nm_Oct2020/interfaces.mdwn
+++ b/180nm_Oct2020/interfaces.mdwn
@@ -1,5 +1,7 @@
 # Interfaces for the 180nm Oct2020 ASIC
 
+http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-May/006355.html
+
 Bugreport and discussion at <https://bugs.libre-soc.org/show_bug.cgi?id=304>
 
 These are bare minimum viability:
@@ -19,4 +21,22 @@ Under consideration:
 
 # Secondary priorities
 
+* a PLL (this is quite a lot however it turns the ASIC from a 24mhz
+design into a 300mhz design)
+* a TLB and MMU (in combination with a PLL if it is GNU/Linux OS
+capable we have an actual viable *saleable product*, immediately)
+* dual L1 Caches with the 2x 128-bit-wide L0CacheBuffer to merge 8x LD/STs
+* multiple Common Data Buses to / from the RegFile along with a 4x
+"Striped" HI/LO-32-ODD/EVEN access pattern.
+* multi-issue
+* PartitionedSignal-based integer pipelines
+* an FP regfile and associated FP pipelines
+* SV compliance
+* 128x INT/FP registers
+* GPU-style opcodes - Jacob you mentioned Texturisation opcodes as
+being more important than e.g. SIN/COS.
+* additional interfaces such as RGB/TTL, SDRAM, HyperRAM, RGMII,
+SD/MMC, USB-ULPI
+* a pinmux
+
 TODO