Forgot the Makefile, stupid!

diff --git a/experiments9/tsmc_c018/Makefile b/experiments9/tsmc_c018/Makefile
new file mode 100755 (executable)
index 0000000..c24742d
--- /dev/null
+++ b/experiments9/tsmc_c018/Makefile
@@ -0,0 +1,48 @@
+
+        LOGICAL_SYNTHESIS = Yosys
+       PHYSICAL_SYNTHESIS = Coriolis
+               DESIGN_KIT = FlexLib018
+#              DESIGN_KIT = cmos45
+             YOSYS_FLATTEN = No
+#            YOSYS_SET_TOP = Yes
+                    CHIP  = chip
+                    CORE  = ls180
+            USE_CLOCKTREE = Yes
+                USE_DEBUG = No
+                 RM_CHIP  = Yes
+                VST_FLAGS = --vst-no-lowercase
+
+                 #NETLISTS = $(shell cat cells.lst)
+                 NETLISTS = ls180
+#            YOSYS_FLATTEN = $(shell cat flatten.lst)
+
+ include ./mk/design-flow.mk
+
+chip_r.vst: ls180.vst
+       -$(call scl_cols,$(call c2env, cgt -tV --script=doDesign))
+
+chip_r.ap: chip_r.vst
+
+pinmux:
+       (cd coriolis2 && python ../../../pinmux/src/pinmux_generator.py -v -s ls180 -o ls180)
+       ln -f -s ../../../pinmux/src/parse.py coriolis2/pinparse.py
+       ln -f -s coriolis2/ls180 ls180
+
+# comment out for now
+blif:      ls180.blif
+vst:       ls180.vst
+
+lvx:       lvx-chip_r
+druc:      druc-chip_r
+dreal:     dreal-chip_r
+flatph:     flatph-chip_r
+view:      cgt-chip_r
+
+layout:    chip_r.ap
+gds:       chip_r.gds
+gds_flat:  chip_r_flat.gds
+cif:      chip_r.cif
+
+
+view:      cgt-chip_r
+sim:       asimut-ls180_r