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+Message-ID: <686f9b58ae6f6a3e11caff9714db66a0406e8b0b.camel@lip6.fr>
+From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
+To: Libre-RISCV General Development <libre-riscv-dev@lists.libre-riscv.org>
+Date: Tue, 24 Mar 2020 13:23:36 +0100
+In-Reply-To: <0F80A1BC-0241-49FE-B374-B4F1D8F3F5BD@gatech.edu>
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+Subject: Re: [libre-riscv-dev] Advanced Topics on RISCV
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+
+
+Hello Immanuel,
+
+About manycores, we did a lot of work on that topic in our lab
+(Sorbonne Universit=C3=A9/LIP6). I send you a reference toward the
+project we developed. This is a huge lot of work and may take
+a lot of time to understand. But, we made a real chip with
+16 cores to prove it works (and it do work). I cannot give you
+more technical information as it not my field of expertise.
+
+You must distinguish two case:
+
+* Multi cores ( < 16) in that case, simpler solutions can be
+ used.
+
+* Many cores ( > 16) in this case, the TSAR project can be
+ of interest.
+
+TSAR (Tera-Scale ARchitecture).
+
+You can see details here:
+ https://www-soc.lip6.fr/trac/tsar
+
+Best regards,
+
+
+PS: Already signaled it to Luke.
+
+
+On Tue, 2020-03-24 at 11:51 +0000, Immanuel, Yehowshua U wrote:
+> I=E2=80=99ve read through the Spike page and a good portion of the simple=
+V page.
+>=20
+> My two goals at the moment are:
+> 1. Understand how RISCV handles multiple processes and does page walking
+> 2. Understand how multicore ROSCV would work
+>=20
+> I=E2=80=99m hoping to play with FreeRTOS soon so I can run through its co=
+debase for setting up
+> page tables.
+> Also, do you know if spike tests the special instructions like exception =
+instructions?
+> Also, what RISCV instructions would a kernel use to set up the pagetables=
+?
+>=20
+> Lastly, do you know any good resources for intro to multicore systems? RI=
+SCV doesn=E2=80=99t
+> seem to have any multicore specific instructions. My current questions wo=
+uld include
+> things like:
+>=20
+> 1. How can the kernel assign tasks to a certain core? If you have a proce=
+ss with
+> multiple threads, it would make sense to spread out the threads among ava=
+ilable
+> processors instead of concentrating them on a single core. How might this=
+ work with
+> respect to RISCV?
+>=20
+> 2. Does the hardware ensure cache coherency - that is - externally - soft=
+ware sees one
+> big cache all though I imagine each core would have a local cache that wo=
+uld have to
+> communicate with other caches?
+>=20
+> Yehowshua
+> _______________________________________________
+> libre-riscv-dev mailing list
+> libre-riscv-dev@lists.libre-riscv.org
+> http://lists.libre-riscv.org/mailman/listinfo/libre-riscv-dev
+--=20
+
+ .-. J e a n - P a u l C h a p u t / Administrateur Systeme
+ /v\ Jean-Paul.Chaput@lip6.fr
+ /(___)\ work: (33) 01.44.27.53.99 =20
+ ^^ ^^ cell: 06.66.25.35.55 home: 09.65.29.83.38
+
+ U P M C Universite Pierre & Marie Curie
+ L I P 6 Laboratoire d'Informatique de Paris VI
+ S o C System On Chip
+
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projects / libre-riscv-dev.git / commitdiff