wire out signals needed for verilator simulation

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 1da6b3fb331d04ab7a774c4bfa410ecf70548e9e..8a3ad3a7d35f51c9695acf82e52d325bd611d580 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -36,7 +36,15 @@ entity toplevel is
     bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0);
     bram_di   : inout std_logic_vector(63 downto 0);
     bram_do   : out std_logic_vector(63 downto 0);
-    bram_sel  : out std_logic_vector(7 downto 0)
+    bram_sel  : out std_logic_vector(7 downto 0);
+    
+    -- for verilator debugging
+    nia_req: out std_ulogic;
+    nia: out std_ulogic_vector(63 downto 0);
+    msr_o: out std_ulogic_vector(63 downto 0);
+    insn: out std_ulogic_vector(31 downto 0);
+    ldst_req: out std_ulogic;
+    ldst_addr: out std_ulogic_vector(63 downto 0)
        );
 end entity toplevel;
 
@@ -104,7 +112,13 @@ begin
         bram_addr           => bram_addr,
         bram_di             => bram_di,
         bram_do             => bram_do,
-        bram_sel            => bram_sel
+        bram_sel            => bram_sel,
+        nia_req           => nia_req,
+        nia               => nia,
+        msr_o             => msr_o,
+        insn              => insn,
+        ldst_req          => ldst_req,
+        ldst_addr         => ldst_addr
            );
 
 end architecture behaviour;