add standards tag

diff --git a/nlnet_proposals.mdwn b/nlnet_proposals.mdwn
index cf584ace3e50ac63f6551eb841891f477b16fcb3..384b35dec2ba445bd77425aa613cf926631e15a2 100644 (file)
--- a/nlnet_proposals.mdwn
+++ b/nlnet_proposals.mdwn
@@ -9,7 +9,7 @@
   added RADV, re-submitted 2019sep26
 * [[nlnet_2019_gcc]] - submitted 2019sep23
 * [[nlnet_2019_wishbone_streaming]] - submitted 2019sep26
-* [[nlnet_2019_standards]] - submitted 2019sep27
+* [[nlnet_2019_standards]] - submitted 2019sep27 - submitter found (phcomp)
 
 # MESA RADV Discussion links
 

diff --git a/resources.mdwn b/resources.mdwn
index ba4b5b694902d5d57b6c08ae650312d2fe49fc1e..e5a46b09f704fe4fea325e8ae0de849a11dc9f9b 100644 (file)
--- a/resources.mdwn
+++ b/resources.mdwn
@@ -4,6 +4,13 @@ This page aims to collect all the resources and specifications we need
 in one place for quick access. We will try our best to keep links here
 up-to-date. Feel free to add more links here.
 
+# Libre-RISC-V Standards
+
+This list auto-generated from a page tag "standards":
+
+[[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
+
+
 # RISC-V Instruction Set Architecture
 
 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 8e6bbc27e38d8381693805c86fecd825bb1f9994..09cbf340cd6c5dedcebcf295e2fc5a3408d37a4e 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Simple-V (Parallelism Extension Proposal) Specification (Abridged)
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton

diff --git a/simple_v_extension/appendix.mdwn b/simple_v_extension/appendix.mdwn
index 8d8941bcacf93fe752ee72d1653f2b45812f8241..d4a69b3529a925f146827c1de1449e46abd8cb65 100644 (file)
--- a/simple_v_extension/appendix.mdwn
+++ b/simple_v_extension/appendix.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Simple-V (Parallelism Extension Proposal) Appendix
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton

diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn
index dea2ffd36b9f8e33cee079ae00cbbba1f35d94e2..fa86b961d8d40153e14663ba5771a31b0e088081 100644 (file)
--- a/simple_v_extension/specification.mdwn
+++ b/simple_v_extension/specification.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Simple-V (Parallelism Extension Proposal) Specification
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton

diff --git a/simple_v_extension/specification/bitmanip.mdwn b/simple_v_extension/specification/bitmanip.mdwn
index b822e697c4b20b151aab6b993720fd4acf14c05f..6b78aa19876e13927127f64a5f3b094bc43c16be 100644 (file)
--- a/simple_v_extension/specification/bitmanip.mdwn
+++ b/simple_v_extension/specification/bitmanip.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Bitmanip opcodes
 
 These are bit manipulation opcodes that, if provided, augment SimpleV for

diff --git a/simple_v_extension/specification/mv.x.rst b/simple_v_extension/specification/mv.x.rst
index 49d9144b35fe1bc89e611a4b50925712ab9daa93..bd668abaaf2809ce84753d07ec91cbc2588514b7 100644 (file)
--- a/simple_v_extension/specification/mv.x.rst
+++ b/simple_v_extension/specification/mv.x.rst
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 MV.X and MV.swizzle
 ===================
 

diff --git a/simple_v_extension/specification/sv.setvl.mdwn b/simple_v_extension/specification/sv.setvl.mdwn
index 80d6296c57bae6b936bd2b8c3357bd32aa214e79..a7eea7a9888188364e99fc401a55a7f816e4f94b 100644 (file)
--- a/simple_v_extension/specification/sv.setvl.mdwn
+++ b/simple_v_extension/specification/sv.setvl.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # SV setvl
 
 sv.setvl allows optional setting of both MVL and of indirectly marking

diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index 6e67b1ca35752fbda93d1f5121ea0fe7e5aacde4..8260fee9e3630bbe5758c6fad7066a0ee960c24c 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 SimpleV Prefix (SVprefix) Proposal v0.3
 =======================================
 

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index 413dcd5dce3adbdd6fc38cbba40aa926fa059619..c996b3955400d850e1e2f4b3c5931f1f4be4906f 100644 (file)
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Simple-V (Parallelism Extension Proposal) Vector Block Format
 
 * Copyright (C) 2017, 2018, 2019 Luke Kenneth Casson Leighton

diff --git a/simple_v_extension/vector_ops.mdwn b/simple_v_extension/vector_ops.mdwn
index 0367f5c56ebb40dd93e8ff4a74f855a2fc279f99..aa4b3f0018b5e4ab9da892ab3213f0f9b62463d2 100644 (file)
--- a/simple_v_extension/vector_ops.mdwn
+++ b/simple_v_extension/vector_ops.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Vector Operations Extension to SV
 
 This extension is usually dependent on SV SUBVL being implemented. When SUBVL is set to define the length of a subvector the operations in this extension interpret the elements as a single vector.

diff --git a/zfpacc_proposal.mdwn b/zfpacc_proposal.mdwn
index 96cdc8e2f08ea5dbd988a1929c3a37019d677b90..4262c53f941ff770a76d25a34263267af4ad2560 100644 (file)
--- a/zfpacc_proposal.mdwn
+++ b/zfpacc_proposal.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # FP Accuracy proposal
 
 Credits:

diff --git a/ztrans_proposal.mdwn b/ztrans_proposal.mdwn
index 5e2685850779d2e19251704dda8e7a88c1716a98..ac805a542f6cbb75a345a09be9bebd422294c1ed 100644 (file)
--- a/ztrans_proposal.mdwn
+++ b/ztrans_proposal.mdwn
@@ -1,3 +1,5 @@
+[[!tag standards]]
+
 # Zftrans - transcendental operations
 
 Summary: