boards/platforms/versa_ecp5: fix mising update.

diff --git a/litex/boards/platforms/versa_ecp5.py b/litex/boards/platforms/versa_ecp5.py
index 4ea3df466fa55368d377079213bf5e6a0f1aa1b4..4ab2383074b35df8b2f1cc2567577fe40e7f91d0 100644 (file)
--- a/litex/boards/platforms/versa_ecp5.py
+++ b/litex/boards/platforms/versa_ecp5.py
@@ -221,8 +221,9 @@ class Platform(LatticePlatform):
     default_clk_name   = "clk100"
     default_clk_period = 1e9/100e6
 
-    def __init__(self, **kwargs):
-        LatticePlatform.__init__(self, "LFE5UM5G-45F-8BG381C", _io, _connectors, **kwargs)
+    def __init__(self, device="LFE5UM5G", **kwargs):
+        assert device in ["LFE5UM5G", "LFE5UM"]
+        LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs)
 
     def create_programmer(self):
         return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")