(no commit message)

diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index 3c94ca182b10092bd011ea8f00f62165762da8a6..9298ed998f4f9a8d2ec338f5cfe22a0a43510def 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -47,12 +47,7 @@ Table of contents
 Simple-V is a type of Vectorization best described as a "Prefix Loop
 Subsystem" similar to the 5 decades-old Zilog Z80 `LDIR`[^bib_ldir] instruction and
 to the 8086 `REP`[^bib_rep] Prefix instruction.  More advanced features are similar
-to the Z80 `CPIR`[^bib_cpir] instruction. If naively viewed one-dimensionally as an
-actual Vector ISA it introduces over 1.5 million 64-bit True-Scalable
-Vector instructions on the SFFS Subset and closer to 10 million 64-bit
-True-Scalable Vector instructions if introduced on VSX.  SVP64, the
-instruction format used by Simple-V, is therefore best viewed as an
-orthogonal RISC-paradigm "Loop Prefixing" subsystem instead.
+to the Z80 `CPIR`[^bib_cpir] instruction.
 
 [^bib_ldir]:  [Zilog Z80 LDIR](http://z80-heaven.wikidot.com/instructions-set:ldir)
 [^bib_cpir]:  [Zilog Z80 CPIR](http://z80-heaven.wikidot.com/instructions-set:cpir)
@@ -129,8 +124,11 @@ only 24 bits:
 Different classes of operations require different formats. The earlier
 sections cover the common formats and the five separate modes have their own
 section later:
-CR operations (crops), Arithmetic/Logical (termed "normal"), Load/Store
-Immediate, Load/Store Indexed, and Branch-Conditional.
+* CR operations (crops),
+* Arithmetic/Logical (termed "normal"),
+* Load/Store Immediate,
+* Load/Store Indexed,
+* Branch-Conditional.
 
 ## Definition of Reserved in this spec.