spelling fixes

diff --git a/openpower/sv/rfc/ls006.mdwn b/openpower/sv/rfc/ls006.mdwn
index 1d7b3bb49c95031e50bea3dec40a1857ee753643..dbff804dc9f944e601a23c3855699cfff0420ac0 100644 (file)
--- a/openpower/sv/rfc/ls006.mdwn
+++ b/openpower/sv/rfc/ls006.mdwn
@@ -71,7 +71,7 @@ implements each variant.
 **Notes and Observations**:
 
 * These instructions are present in many other ISAs.
-* Javascript rounding as one instruction saves 35 instructions including
+* JavaScript rounding as one instruction saves 35 instructions including
   six branches.
 
 **Changes**
@@ -144,7 +144,7 @@ Tables that are used by `fmvtg`/`fmvfg`/`fcvttg`/`fcvtfg`:
 ```
 
 Move a 32/64-bit float from a FPR to a GPR, just copying bits of the
-IEEE754 representation directly. This is equivalent to `stfs` followed
+IEEE 754 representation directly. This is equivalent to `stfs` followed
 by `lwz` or equivalent to `stfd` followed by `ld`.  As `fmvtg` is just
 copying bits, `FPSCR` is not affected in any way.
 
@@ -330,7 +330,7 @@ languages (not necessarily for the default conversion method):
 
 * Java's
   [FP -> Integer conversion](https://docs.oracle.com/javase/specs/jls/se16/html/jls-5.html#jls-5.1.3)
-  (only for ling/int results)
+  (only for long/int results)
 * Rust's FP -> Integer conversion using the
   [`as` operator](https://doc.rust-lang.org/reference/expressions/operator-expr.html#semantics)
 * LLVM's