ppc-opc: sync instructions

diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 0b7cffedb9433794f5cad0f81249925df6d89932..43579b2a5c36c34e13d27c77dae25a92639e235e 100644 (file)
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3749,6 +3749,7 @@ const struct powerpc_operand powerpc_operands[] =
 
   /* The 3-bit UIMM field in a VX form instruction.  */
 #define UIMM3 UIMM + 1
+#define CVM UIMM3
   { 0x7, 16, NULL, NULL, 0 },
 
   /* The 6-bit UIM field in a X form instruction.  */
@@ -3856,6 +3857,7 @@ const struct powerpc_operand powerpc_operands[] =
 
 #define SP PRS + 1
 #define mi0 SP
+#define IT SP
   { 0x3, 19, NULL, NULL, 0 },
 
 #define S SP + 1
@@ -5035,7 +5037,7 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
    | (((uint64_t)(rc)) & 1))
 #define MM_MASK        MM (0x3f, 0x3f, 0x1)
 
-/* An MM form instruction with explicit . */
+/* An MM form instruction with explicit MMM. */
 #define MMXMMM(op, xop, mmm, rc)               \
   (OP (op)                                     \
    | ((((uint64_t)(mmm)) & 0x7) << 8)          \
@@ -6578,22 +6580,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"addpcis",  DX(19,2),         DX_MASK,     POWER9,    PPCVLE,         {RT, DXD}},
 {"subpcis",  DX(19,2),         DX_MASK,     POWER9,    PPCVLE|EXT,     {RT, NDXD}},
 
-{"minu",       MMXMMM(19,3,0,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"minu.",      MMXMMM(19,3,0,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxu",       MMXMMM(19,3,1,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxu.",      MMXMMM(19,3,1,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"mins",       MMXMMM(19,3,2,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"mins.",      MMXMMM(19,3,2,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxs",       MMXMMM(19,3,3,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxs.",      MMXMMM(19,3,3,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"minuw",      MMXMMM(19,3,4,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"minuw.",     MMXMMM(19,3,4,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxuw",      MMXMMM(19,3,5,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxuw.",     MMXMMM(19,3,5,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"minsw",      MMXMMM(19,3,6,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"minsw.",     MMXMMM(19,3,6,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxsw",      MMXMMM(19,3,7,0),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
-{"maxsw.",     MMXMMM(19,3,7,1),       MMXMMM_MASK,    SFFS,   PPCVLE, {RT, RA0, RB}},
 {"minmax",     MM(19,3,0),             MM_MASK,        SFFS,   PPCVLE, {RT, RA0, RB, MMM}},
 {"minmax.",    MM(19,3,1),             MM_MASK,        SFFS,   PPCVLE, {RT, RA0, RB, MMM}},
 
@@ -9552,30 +9538,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"facoshs.",   XRC(59,686,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fatanhs",    XRC(59,687,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fatanhs.",   XRC(59,687,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
-{"fminnum08s", XRC(59,716,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminnum08s.",        XRC(59,716,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmin19s",    XRC(59,717,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmin19s.",   XRC(59,717,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminnum19s", XRC(59,718,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminnum19s.",        XRC(59,718,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmincs",     XRC(59,719,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmincs.",    XRC(59,719,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum08s", XRC(59,748,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum08s.",        XRC(59,748,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmax19s",    XRC(59,749,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmax19s.",   XRC(59,749,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum19s", XRC(59,750,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum19s.",        XRC(59,750,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxcs",     XRC(59,751,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxcs.",    XRC(59,751,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fexp2m1s",   XRC(59,780,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexp2m1s.",  XRC(59,780,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2p1s",   XRC(59,781,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2p1s.",  XRC(59,781,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
-{"fminmagnum08s",      XRC(59,782,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagnum08s.",     XRC(59,782,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum08s",      XRC(59,783,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum08s.",     XRC(59,783,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
+{"ctfprs", XRC(59,783,0), X_MASK, SFFS, PPCVLE, {FRT,RB,IT}},
+{"ctfprs.", XRC(59,783,1), X_MASK, SFFS, PPCVLE, {FRT,RB,IT}},
 {"fexpm1s",    XRC(59,812,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexpm1s.",   XRC(59,812,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flogp1s",    XRC(59,813,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
@@ -9590,18 +9558,13 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fpowns.",    XRC(59,876,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, RB}},
 {"frootns",    XRC(59,877,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, RB}},
 {"frootns.",   XRC(59,877,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, RB}},
-{"fminmag19s", XRC(59,878,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmag19s.",        XRC(59,878,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmag19s", XRC(59,879,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmag19s.",        XRC(59,879,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fexp2s",     XRC(59,908,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexp2s.",    XRC(59,908,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2s",     XRC(59,909,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2s.",    XRC(59,909,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
-{"fminmagnum19s",      XRC(59,910,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagnum19s.",     XRC(59,910,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum19s",      XRC(59,911,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum19s.",     XRC(59,911,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
+{"mffprs", XRC(59,910,0), X_MASK, SFFS, PPCVLE, {RT,FRB}},
+{"mffprs.", XRC(59,910,1), X_MASK, SFFS, PPCVLE, {RT,FRB}},
+{"mtfprs", X(59,911), X_MASK, SFFS, PPCVLE, {FRT,RB}},
 {"fexps",      XRC(59,940,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexps.",     XRC(59,940,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flogs",      XRC(59,941,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
@@ -9618,10 +9581,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fpowrs.",    XRC(59,1004,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fpows",      XRC(59,1005,0), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fpows.",     XRC(59,1005,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagcs",  XRC(59,1006,0), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagcs.", XRC(59,1006,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagcs",  XRC(59,1007,0), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagcs.", XRC(59,1007,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 
 {"xsaddsp",    XX3(60,0),      XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
 {"xsmaddasp",  XX3(60,1),      XX3_MASK,    PPCVSX2,   PPCVLE,         {XT6, XA6, XB6}},
@@ -9881,6 +9840,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fctiwz.",    XRC(63,15,1),   XRA_MASK,    PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRB}},
 {"fcirz.",     XRC(63,15,1),   XRA_MASK,    PWR2COM,   PPCVLE,         {FRT, FRB}},
 
+{"fminmax", MM(63,16,0), MM_MASK, SFFS, PPCVLE, {FRT,FRA,FRB,FMM}},
+{"fminmax.", MM(63,16,1), MM_MASK, SFFS, PPCVLE, {FRT,FRA,FRB,FMM}},
+
 {"fdiv",       A(63,18,0),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
 {"fd",         A(63,18,0),     AFRC_MASK,   PWRCOM,    PPCVLE,         {FRT, FRA, FRB}},
 {"fdiv.",      A(63,18,1),     AFRC_MASK,   PPCCOM,    PPCEFS|PPCVLE,  {FRT, FRA, FRB}},
@@ -10022,6 +9984,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fabs",       XRC(63,264,0),  XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
 {"fabs.",      XRC(63,264,1),  XRA_MASK,    COM,       PPCEFS|PPCVLE,  {FRT, FRB}},
 
+{"cffpr", XO(63,270,0,0), XO_MASK, SFFS, PPCVLE, {RT,FRB,CVM,IT}},
+{"cffpr.", XO(63,270,0,1), XO_MASK, SFFS, PPCVLE, {RT,FRB,CVM,IT}},
+
 {"dctfixq",    XRC(63,290,0),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRBp}},
 {"dctfixq.",   XRC(63,290,1),  X_MASK,      POWER6,    PPCVLE,         {FRT, FRBp}},
 
@@ -10148,6 +10113,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 {"xsiexpqp",   X(63,868),      X_MASK,      PPCVSX3,   PPCVLE,         {VD, VA, VB}},
 
+{"mffpr", XRC(63,910,0), X_MASK, SFFS, PPCVLE, {RT,FRB}},
+{"mffpr.", XRC(63,910,1), X_MASK, SFFS, PPCVLE, {RT,FRB}},
+{"mtfpr", X(63,911), X_MASK, SFFS, PPCVLE, {FRT,RB}},
+
 {"fctidu",     XRC(63,942,0),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
 {"fctidu.",    XRC(63,942,1),  XRA_MASK, POWER7|PPCA2, PPCVLE,         {FRT, FRB}},
 
@@ -10210,30 +10179,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"facosh.",    XRC(63,686,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fatanh",     XRC(63,687,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fatanh.",    XRC(63,687,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
-{"fminnum08",  XRC(63,716,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminnum08.", XRC(63,716,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmin19",     XRC(63,717,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmin19.",    XRC(63,717,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminnum19",  XRC(63,718,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminnum19.", XRC(63,718,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminc",      XRC(63,719,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminc.",     XRC(63,719,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum08",  XRC(63,748,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum08.", XRC(63,748,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmax19",     XRC(63,749,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmax19.",    XRC(63,749,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum19",  XRC(63,750,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxnum19.", XRC(63,750,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxc",      XRC(63,751,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxc.",     XRC(63,751,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fexp2m1",    XRC(63,780,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexp2m1.",   XRC(63,780,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2p1",    XRC(63,781,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2p1.",   XRC(63,781,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
-{"fminmagnum08",       XRC(63,782,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagnum08.",      XRC(63,782,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum08",       XRC(63,783,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum08.",      XRC(63,783,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
+{"cffpro", XO(63,782,1,0), XO_MASK, SFFS, PPCVLE, {RT,FRB,CVM,IT}},
+{"cffpro.", XO(63,782,1,1), XO_MASK, SFFS, PPCVLE, {RT,FRB,CVM,IT}},
+{"ctfpr", XRC(63,783,0), X_MASK, SFFS, PPCVLE, {FRT,RB,IT}},
+{"ctfpr.", XRC(63,783,1), X_MASK, SFFS, PPCVLE, {FRT,RB,IT}},
 {"fexpm1",     XRC(63,812,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexpm1.",    XRC(63,812,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flogp1",     XRC(63,813,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
@@ -10248,18 +10201,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fpown.",     XRC(63,876,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, RB}},
 {"frootn",     XRC(63,877,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, RB}},
 {"frootn.",    XRC(63,877,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, RB}},
-{"fminmag19",  XRC(63,878,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmag19.", XRC(63,878,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmag19",  XRC(63,879,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmag19.", XRC(63,879,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fexp2",      XRC(63,908,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexp2.",     XRC(63,908,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2",      XRC(63,909,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog2.",     XRC(63,909,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
-{"fminmagnum19",       XRC(63,910,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagnum19.",      XRC(63,910,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum19",       XRC(63,911,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagnum19.",      XRC(63,911,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fexp",       XRC(63,940,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"fexp.",      XRC(63,940,1),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
 {"flog",       XRC(63,941,0),  X_MASK, SFFS,   PPCVLE, {FRT, FRB}},
@@ -10274,10 +10219,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 {"fpowr.",     XRC(63,1004,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fpow",       XRC(63,1005,0), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 {"fpow.",      XRC(63,1005,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagc",   XRC(63,1006,0), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fminmagc.",  XRC(63,1006,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagc",   XRC(63,1007,0), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
-{"fmaxmagc.",  XRC(63,1007,1), X_MASK, SFFS,   PPCVLE, {FRT, FRA, FRB}},
 };
 
 const unsigned int powerpc_num_opcodes = ARRAY_SIZE (powerpc_opcodes);