RISC-V: Add support for the Zvkg ISA extension

Zvkg is part of the vector crypto extensions.

This extension adds the following instructions:
- vghsh.vv
- vgmul.vv

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvkg.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvkg.d: New test.
	* testsuite/gas/riscv/zvkg.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VGHSH_VV): New.
	(MASK_VGHSH_VV): New.
	(MATCH_VGMUL_VV): New.
	(MASK_VGMUL_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvkg.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvkg instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 295e0d2c942624857aa505d8d73f8b1ed36a9c0c..84461490835da532c6d51ef5ab1c1a53939094a2 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1264,6 +1264,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zve64d",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvbb",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvbc",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zvkg",             ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl32b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl64b",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zvl128b",          ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -2433,6 +2434,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
       return riscv_subset_supports (rps, "zvbb");
     case INSN_CLASS_ZVBC:
       return riscv_subset_supports (rps, "zvbc");
+    case INSN_CLASS_ZVKG:
+      return riscv_subset_supports (rps, "zvkg");
     case INSN_CLASS_SVINVAL:
       return riscv_subset_supports (rps, "svinval");
     case INSN_CLASS_H:
@@ -2625,6 +2628,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("zvbb");
     case INSN_CLASS_ZVBC:
       return _("zvbc");
+    case INSN_CLASS_ZVKG:
+      return _("zvkg");
     case INSN_CLASS_SVINVAL:
       return "svinval";
     case INSN_CLASS_H:

diff --git a/gas/testsuite/gas/riscv/zvkg.d b/gas/testsuite/gas/riscv/zvkg.d
new file mode 100644 (file)
index 0000000..7f898d3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.d
@@ -0,0 +1,10 @@
+#as: -march=rv64gc_zvkg
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+0+000 <.text>:
+[      ]+[0-9a-f]+:[   ]+b2862277[     ]+vghsh.vv[     ]+v4,v8,v12
+[      ]+[0-9a-f]+:[   ]+a2c8a277[     ]+vgmul.vv[     ]+v4,v12

diff --git a/gas/testsuite/gas/riscv/zvkg.s b/gas/testsuite/gas/riscv/zvkg.s
new file mode 100644 (file)
index 0000000..b802d6a
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvkg.s
@@ -0,0 +1,2 @@
+       vghsh.vv v4, v8, v12
+       vgmul.vv v4, v12

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 6102feaa5577f4565f67938d31a0d769345020da..8b4b3b2662ce24b68ea053804f4faf320b84bd6a 100644 (file)
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2163,6 +2163,11 @@
 #define MASK_VCLMULH_VV 0xfc00707f
 #define MATCH_VCLMULH_VX 0x34006057
 #define MASK_VCLMULH_VX 0xfc00707f
+/* Zvkg instructions.  */
+#define MATCH_VGHSH_VV 0xb2002077
+#define MASK_VGHSH_VV 0xfe00707f
+#define MATCH_VGMUL_VV 0xa208a077
+#define MASK_VGMUL_VV 0xfe0ff07f
 /* Svinval instruction.  */
 #define MATCH_SINVAL_VMA 0x16000073
 #define MASK_SINVAL_VMA 0xfe007fff
@@ -3294,6 +3299,9 @@ DECLARE_INSN(vclmul_vv, MATCH_VCLMUL_VV, MASK_VCLMUL_VV)
 DECLARE_INSN(vclmul_vx, MATCH_VCLMUL_VX, MASK_VCLMUL_VX)
 DECLARE_INSN(vclmulh_vv, MATCH_VCLMULH_VV, MASK_VCLMULH_VV)
 DECLARE_INSN(vclmulh_vx, MATCH_VCLMULH_VX, MASK_VCLMULH_VX)
+/* Zvkg instructions.  */
+DECLARE_INSN(vghsh_vv, MATCH_VGHSH_VV, MASK_VGHSH_VV)
+DECLARE_INSN(vgmul_vv, MATCH_VGMUL_VV, MASK_VGMUL_VV)
 /* Vendor-specific (T-Head) XTheadBa instructions.  */
 DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
 /* Vendor-specific (T-Head) XTheadBb instructions.  */

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 783b1c01e52cfd17f6caec708baa14f46dd53586..b2098867a19b8b0fc1e992c0d842ca1012563566 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -416,6 +416,7 @@ enum riscv_insn_class
   INSN_CLASS_ZVEF,
   INSN_CLASS_ZVBB,
   INSN_CLASS_ZVBC,
+  INSN_CLASS_ZVKG,
   INSN_CLASS_SVINVAL,
   INSN_CLASS_ZICBOM,
   INSN_CLASS_ZICBOP,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 19a72903510c25ede928d05f6cb73d0025c4e0fb..b2aadb1bc797e2d0a031a061fcacc81eaee5fca3 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -1908,6 +1908,10 @@ const struct riscv_opcode riscv_opcodes[] =
 {"vclmulh.vv",   0, INSN_CLASS_ZVBC, "Vd,Vt,VsVm", MATCH_VCLMULH_VV, MASK_VCLMULH_VV, match_opcode, 0},
 {"vclmulh.vx",   0, INSN_CLASS_ZVBC, "Vd,Vt,sVm", MATCH_VCLMULH_VX, MASK_VCLMULH_VX, match_opcode, 0},
 
+/* Zvkg instructions.  */
+{"vghsh.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt,Vs", MATCH_VGHSH_VV, MASK_VGHSH_VV, match_opcode, 0},
+{"vgmul.vv",   0, INSN_CLASS_ZVKG, "Vd,Vt", MATCH_VGMUL_VV, MASK_VGMUL_VV, match_opcode, 0},
+
 /* Supervisor instructions.  */
 {"csrr",       0, INSN_CLASS_ZICSR, "d,E",   MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },
 {"csrw",       0, INSN_CLASS_ZICSR, "E,s",   MATCH_CSRRW, MASK_CSRRW|MASK_RD, match_opcode, INSN_ALIAS },