add I-Cache to FSM local variables

diff --git a/src/soc/config/ifetch.py b/src/soc/config/ifetch.py
index a73a89bc6c5b2fe8962d0072a0b2939010ffd3fe..a40c272704752db2fd2f23284389aea3d13239a2 100644 (file)
--- a/src/soc/config/ifetch.py
+++ b/src/soc/config/ifetch.py
@@ -21,3 +21,6 @@ class ConfigFetchUnit:
         fukls = fudict[pspec.imem_ifacetype]
         self.fu = fukls(pspec)
 
+    def wb_bus(self):
+        return self.fu.ibus
+

diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index ae71f97b80fac3090629117e6b92dbe4e4c31a4a..7e8a699ff5de7235baac372260703275828e0d30 100644 (file)
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -65,6 +65,7 @@ class FSMMMUStage(ControlBase):
         # incoming PortInterface
         self.ldst = ldst
         self.dcache = self.ldst.dcache
+        self.icache = self.ldst.icache
         self.pi = self.ldst.pi
 
     def elaborate(self, platform):