arch-power: Add fixed-point load and reserve instructions

This adds the following load instructions:
  * Load Byte And Reserve Indexed (lbarx)
  * Load Halfword And Reserve Indexed (lharx)
  * Load Doubleword And Reserve Indexed (ldarx)

Change-Id: Iac3cf0e16e2b5da8b772be81850419e21f26bdab
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 20d1f741b19dbb6f74458d425fd63f939c2c4db0..2c1ecf2d5aa9ea0e733271387f127acbaa454de0 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -264,14 +264,17 @@ decode PO default Unknown::unknown() {
         // Ra and Rb are source registers, Rt is the destintation.
         format LoadIndexOp {
             87: lbzx({{ Rt = Mem_ub; }});
+            52: lbarx({{ Rt = Mem_ub; Rsv = 1; RsvLen = 1; RsvAddr = EA; }});
             279: lhzx({{ Rt = Mem_uh; }});
             343: lhax({{ Rt = Mem_sh; }});
+            116: lharx({{ Rt = Mem_uh; Rsv = 1; RsvLen = 2; RsvAddr = EA; }});
             790: lhbrx({{ Rt = swap_byte(Mem_uh); }});
             23: lwzx({{ Rt = Mem_uw; }});
             341: lwax({{ Rt = Mem_sw; }});
             20: lwarx({{ Rt = Mem_uw; Rsv = 1; RsvLen = 4; RsvAddr = EA; }});
             534: lwbrx({{ Rt = swap_byte(Mem_uw); }});
             21: ldx({{ Rt = Mem; }});
+            84: ldarx({{ Rt = Mem_ud; Rsv = 1; RsvLen = 8; RsvAddr = EA; }});
             532: ldbrx({{ Rt = swap_byte(Mem); }});
             535: lfsx({{ Ft_sf = Mem_sf; }});
             599: lfdx({{ Ft = Mem_df; }});