remove MiSoC dependency

diff --git a/README b/README
index 235b36e81f2384edb2beb65709fa3d4b5a4d8e03..025c46c43390f2f834bdf9041ac8d30196c769f5 100644 (file)
--- a/README
+++ b/README
@@ -81,27 +81,20 @@ devel [AT] lists.m-labs.hk.
   python3 setup.py install
   cd ..
 
-3. Obtain MiSoC and install it:
-  git clone https://github.com/m-labs/misoc --recursive
-  cd misoc
-  python3 setup.py install
-  cd ..
-
-Note: in case you have issues with Migen/MiSoC, please retry
+Note: in case you have issues with Migen, please retry
 with our forks at:
-  https://github.com/enjoy-digital/misoc
   https://github.com/enjoy-digital/migen
 until new features are merged.
 
-4. Obtain LiteScope and install it:
+3. Obtain LiteScope and install it:
   git clone https://github.com/enjoy-digital/litescope
 
-5. Build and load test design:
+4. Build and load test design:
   python3 make.py -s [platform] all
-  Supported platforms are the one altready supported by Mibuild:
+  Supported platforms are the ones already supported by Mibuild:
   de0nano, m1, mixxeo, kc705, zedboard...
 
-6. Test design:
+5. Test design:
   go to ./test directory and run:
   python3 test_io.py
   python3 test_la.py

diff --git a/doc/source/docs/getting_started/downloads.rst b/doc/source/docs/getting_started/downloads.rst
index adcea54bf5ca68a877b047a341b61b651a30806c..c50c9ca2cd5d2e76df523ac87b97aab4c4e2d026 100644 (file)
--- a/doc/source/docs/getting_started/downloads.rst
+++ b/doc/source/docs/getting_started/downloads.rst
@@ -11,31 +11,18 @@ Download and install
   - python3 setup.py install
   - cd ..
 
-3. Obtain LiteScope and install it:
-  - git clone https://github.com/enjoy-digital/litescope
-  - cd litescope
-  - python3 setup.py install
-  - cd ..
-
-4. Obtain MiSoC and install it:
-  - git clone https://github.com/m-labs/misoc --recursive
-  - cd misoc
-  - python3 setup.py install
-  - cd ..
-
 .. note::
-       In case you have issues with Migen/MiSoC, please retry with our forks at:
-       https://github.com/enjoy-digital/misoc
+       In case you have issues with Migen, please retry with our forks at:
        https://github.com/enjoy-digital/migen
        until new features are merged.
 
-5. Obtain LiteScope
+3. Obtain LiteScope
   - git clone https://github.com/enjoy-digital/litescope
 
-6. Build and load example design:
+4. Build and load example design:
   - python3 make.py all
 
-7. Test design:
+5. Test design:
   - go to ./test directoryand run:
   - python3 test_io.py
   - python3 test_la.py

diff --git a/make.py b/make.py
index 09058218bd00a4eb1bb13e8ec5665e13921981ec..4fb2238c1c79f1981e0f14ac6396be6f167523e1 100644 (file)
--- a/make.py
+++ b/make.py
@@ -6,13 +6,22 @@ from mibuild.tools import write_to_file
 from migen.util.misc import autotype
 from migen.fhdl import verilog, edif
 from migen.fhdl.structure import _Fragment
+from migen.bank.description import CSRStatus
 from mibuild import tools
 from mibuild.xilinx_common import *
 
-from misoclib.gensoc import cpuif
-
 from litescope.common import *
 
+def get_csr_csv(regions):
+       r = ""
+       for name, origin, busword, obj in regions:
+               if not isinstance(obj, Memory):
+                       for csr in obj:
+                               nr = (csr.size + busword - 1)//busword
+                               r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
+                               origin += 4*nr
+       return r
+
 def _import(default, name):
        return importlib.import_module(default + "." + name)
 
@@ -127,7 +136,7 @@ RLE: {}
                subprocess.call(["rm", "-rf", "build/*"])
 
        if actions["build-csr-csv"]:
-               csr_csv = cpuif.get_csr_csv(soc.cpu_csr_regions)
+               csr_csv = get_csr_csv(soc.cpu_csr_regions)
                write_to_file(args.csr_csv, csr_csv)
 
        if actions["build-bitstream"]:

diff --git a/targets/__init__.py b/targets/__init__.py
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..85efe5d95f5b4b86fef0ca348005cd7a2a2f6c27 100644 (file)
--- a/targets/__init__.py
+++ b/targets/__init__.py
@@ -0,0 +1,26 @@
+import subprocess
+
+from migen.fhdl.std import *
+from migen.bank.description import *
+
+def get_id():
+       output = subprocess.check_output(["git", "rev-parse", "HEAD"]).decode("ascii")
+       return int(output[:8], 16)
+
+class Identifier(Module, AutoCSR):
+       def __init__(self, sysid, frequency, revision=None):
+               self._r_sysid = CSRStatus(16)
+               self._r_revision = CSRStatus(32)
+               self._r_frequency = CSRStatus(32)
+
+               ###
+
+               if revision is None:
+                       revision = get_id()
+
+               self.comb += [
+                       self._r_sysid.status.eq(sysid),
+                       self._r_revision.status.eq(revision),
+                       self._r_frequency.status.eq(frequency),
+               ]
+

diff --git a/targets/simple.py b/targets/simple.py
index 672744f96b913bd8e735021d6b074ea7fffcdcb4..27556fd3b9ae7982859f26527b32a9334603e054 100644 (file)
--- a/targets/simple.py
+++ b/targets/simple.py
@@ -5,7 +5,7 @@ from migen.bus import wishbone, csr
 from migen.bus import wishbone2csr
 from migen.bank.description import *
 
-from misoclib import identifier
+from targets import *
 
 from litescope.common import *
 from litescope.bridge.uart2wb import LiteScopeUART2WB
@@ -48,7 +48,7 @@ class GenSoC(Module):
                self.cpu_csr_regions = [] # list of (name, origin, busword, csr_list/Memory)
 
                # CSR
-               self.submodules.identifier = identifier.Identifier(0, int(clk_freq), 0)
+               self.submodules.identifier = Identifier(0, int(clk_freq))
 
        def add_cpu_memory_region(self, name, origin, length):
                self.cpu_memory_regions.append((name, origin, length))