cpu-o3: convert decode to new style stats

Change-Id: Ia67a51f3b2c2d40d8bf09f1636c721550f5e9a23
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33316
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c705801b88f33916a657a0cb335f709b16829672..c5b4a825f1cfac200b978d0c245393eaeec836ca 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -441,7 +441,6 @@ FullO3CPU<Impl>::regStats()
         .precision(6);
     totalIpc =  sum(committedInsts) / numCycles;
 
-    this->decode.regStats();
     this->rename.regStats();
     this->iew.regStats();
     this->rob.regStats();

diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh
index 9e26bae2dadb2b8ff424308b4876dd6c1059d6a3..c0c0b81b4c1fa43a65de8cd8fa3531be2ac34477 100644 (file)
--- a/src/cpu/o3/decode.hh
+++ b/src/cpu/o3/decode.hh
@@ -109,9 +109,6 @@ class DefaultDecode
     /** Returns the name of decode. */
     std::string name() const;
 
-    /** Registers statistics. */
-    void regStats();
-
     /** Sets the main backwards communication time buffer pointer. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
@@ -295,29 +292,32 @@ class DefaultDecode
      */
     bool squashAfterDelaySlot[Impl::MaxThreads];
 
-
-    /** Stat for total number of idle cycles. */
-    Stats::Scalar decodeIdleCycles;
-    /** Stat for total number of blocked cycles. */
-    Stats::Scalar decodeBlockedCycles;
-    /** Stat for total number of normal running cycles. */
-    Stats::Scalar decodeRunCycles;
-    /** Stat for total number of unblocking cycles. */
-    Stats::Scalar decodeUnblockCycles;
-    /** Stat for total number of squashing cycles. */
-    Stats::Scalar decodeSquashCycles;
-    /** Stat for number of times a branch is resolved at decode. */
-    Stats::Scalar decodeBranchResolved;
-    /** Stat for number of times a branch mispredict is detected. */
-    Stats::Scalar decodeBranchMispred;
-    /** Stat for number of times decode detected a non-control instruction
-     * incorrectly predicted as a branch.
-     */
-    Stats::Scalar decodeControlMispred;
-    /** Stat for total number of decoded instructions. */
-    Stats::Scalar decodeDecodedInsts;
-    /** Stat for total number of squashed instructions. */
-    Stats::Scalar decodeSquashedInsts;
+    struct DecodeStats : public Stats::Group {
+        DecodeStats(O3CPU *cpu);
+
+        /** Stat for total number of idle cycles. */
+        Stats::Scalar idleCycles;
+        /** Stat for total number of blocked cycles. */
+        Stats::Scalar blockedCycles;
+        /** Stat for total number of normal running cycles. */
+        Stats::Scalar runCycles;
+        /** Stat for total number of unblocking cycles. */
+        Stats::Scalar unblockCycles;
+        /** Stat for total number of squashing cycles. */
+        Stats::Scalar squashCycles;
+        /** Stat for number of times a branch is resolved at decode. */
+        Stats::Scalar branchResolved;
+        /** Stat for number of times a branch mispredict is detected. */
+        Stats::Scalar branchMispred;
+        /** Stat for number of times decode detected a non-control instruction
+         * incorrectly predicted as a branch.
+         */
+        Stats::Scalar controlMispred;
+        /** Stat for total number of decoded instructions. */
+        Stats::Scalar decodedInsts;
+        /** Stat for total number of squashed instructions. */
+        Stats::Scalar squashedInsts;
+    } stats;
 };
 
 #endif // __CPU_O3_DECODE_HH__

diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
index cf3d6012cae5759679ec2d4bc3416a14772f7fc9..24640f6a5519372198e98bbbf2c476d18fba6c38 100644 (file)
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -64,7 +64,8 @@ DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
       commitToDecodeDelay(params->commitToDecodeDelay),
       fetchToDecodeDelay(params->fetchToDecodeDelay),
       decodeWidth(params->decodeWidth),
-      numThreads(params->numThreads)
+      numThreads(params->numThreads),
+      stats(_cpu)
 {
     if (decodeWidth > Impl::MaxWidth)
         fatal("decodeWidth (%d) is larger than compiled limit (%d),\n"
@@ -119,50 +120,33 @@ DefaultDecode<Impl>::name() const
 }
 
 template <class Impl>
-void
-DefaultDecode<Impl>::regStats()
+DefaultDecode<Impl>::DecodeStats::DecodeStats(O3CPU *cpu)
+    : Stats::Group(cpu, "decode"),
+      ADD_STAT(idleCycles, "Number of cycles decode is idle"),
+      ADD_STAT(blockedCycles, "Number of cycles decode is blocked"),
+      ADD_STAT(runCycles, "Number of cycles decode is running"),
+      ADD_STAT(unblockCycles, "Number of cycles decode is unblocking"),
+      ADD_STAT(squashCycles, "Number of cycles decode is squashing"),
+      ADD_STAT(branchResolved, "Number of times decode resolved a "
+          " branch"),
+      ADD_STAT(branchMispred, "Number of times decode detected a branch"
+          " misprediction"),
+      ADD_STAT(controlMispred,"Number of times decode detected an"
+          " instruction incorrectly predicted as a control"),
+      ADD_STAT(decodedInsts, "Number of instructions handled by decode"),
+      ADD_STAT(squashedInsts, "Number of squashed instructions handled"
+          " by decode")
 {
-    decodeIdleCycles
-        .name(name() + ".IdleCycles")
-        .desc("Number of cycles decode is idle")
-        .prereq(decodeIdleCycles);
-    decodeBlockedCycles
-        .name(name() + ".BlockedCycles")
-        .desc("Number of cycles decode is blocked")
-        .prereq(decodeBlockedCycles);
-    decodeRunCycles
-        .name(name() + ".RunCycles")
-        .desc("Number of cycles decode is running")
-        .prereq(decodeRunCycles);
-    decodeUnblockCycles
-        .name(name() + ".UnblockCycles")
-        .desc("Number of cycles decode is unblocking")
-        .prereq(decodeUnblockCycles);
-    decodeSquashCycles
-        .name(name() + ".SquashCycles")
-        .desc("Number of cycles decode is squashing")
-        .prereq(decodeSquashCycles);
-    decodeBranchResolved
-        .name(name() + ".BranchResolved")
-        .desc("Number of times decode resolved a branch")
-        .prereq(decodeBranchResolved);
-    decodeBranchMispred
-        .name(name() + ".BranchMispred")
-        .desc("Number of times decode detected a branch misprediction")
-        .prereq(decodeBranchMispred);
-    decodeControlMispred
-        .name(name() + ".ControlMispred")
-        .desc("Number of times decode detected an instruction incorrectly"
-              " predicted as a control")
-        .prereq(decodeControlMispred);
-    decodeDecodedInsts
-        .name(name() + ".DecodedInsts")
-        .desc("Number of instructions handled by decode")
-        .prereq(decodeDecodedInsts);
-    decodeSquashedInsts
-        .name(name() + ".SquashedInsts")
-        .desc("Number of squashed instructions handled by decode")
-        .prereq(decodeSquashedInsts);
+    idleCycles.prereq(idleCycles);
+    blockedCycles.prereq(blockedCycles);
+    runCycles.prereq(runCycles);
+    unblockCycles.prereq(unblockCycles);
+    squashCycles.prereq(squashCycles);
+    branchResolved.prereq(branchResolved);
+    branchMispred.prereq(branchMispred);
+    controlMispred.prereq(controlMispred);
+    decodedInsts.prereq(decodedInsts);
+    squashedInsts.prereq(squashedInsts);
 }
 
 template<class Impl>
@@ -607,9 +591,9 @@ DefaultDecode<Impl>::decode(bool &status_change, ThreadID tid)
     //     check if stall conditions have passed
 
     if (decodeStatus[tid] == Blocked) {
-        ++decodeBlockedCycles;
+        ++stats.blockedCycles;
     } else if (decodeStatus[tid] == Squashing) {
-        ++decodeSquashCycles;
+        ++stats.squashCycles;
     }
 
     // Decode should try to decode as many instructions as its bandwidth
@@ -653,14 +637,14 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         DPRINTF(Decode, "[tid:%i] Nothing to do, breaking out"
                 " early.\n",tid);
         // Should I change the status to idle?
-        ++decodeIdleCycles;
+        ++stats.idleCycles;
         return;
     } else if (decodeStatus[tid] == Unblocking) {
         DPRINTF(Decode, "[tid:%i] Unblocking, removing insts from skid "
                 "buffer.\n",tid);
-        ++decodeUnblockCycles;
+        ++stats.unblockCycles;
     } else if (decodeStatus[tid] == Running) {
-        ++decodeRunCycles;
+        ++stats.runCycles;
     }
 
     std::queue<DynInstPtr>
@@ -684,7 +668,7 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
                     "squashed, skipping.\n",
                     tid, inst->seqNum, inst->pcState());
 
-            ++decodeSquashedInsts;
+            ++stats.squashedInsts;
 
             --insts_available;
 
@@ -706,7 +690,7 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
 
         ++(toRename->size);
         ++toRenameIndex;
-        ++decodeDecodedInsts;
+        ++stats.decodedInsts;
         --insts_available;
 
 #if TRACING_ON
@@ -720,7 +704,7 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         if (inst->readPredTaken() && !inst->isControl()) {
             panic("Instruction predicted as a branch!");
 
-            ++decodeControlMispred;
+            ++stats.controlMispred;
 
             // Might want to set some sort of boolean and just do
             // a check at the end
@@ -735,10 +719,10 @@ DefaultDecode<Impl>::decodeInsts(ThreadID tid)
         if (inst->isDirectCtrl() &&
            (inst->isUncondCtrl() || inst->readPredTaken()))
         {
-            ++decodeBranchResolved;
+            ++stats.branchResolved;
 
             if (!(inst->branchTarget() == inst->readPredTarg())) {
-                ++decodeBranchMispred;
+                ++stats.branchMispred;
 
                 // Might want to set some sort of boolean and just do
                 // a check at the end