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FLGA_TARGET=verilator not uppercase
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 00:41:12 +0000 (00:41 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 15 Feb 2022 00:41:12 +0000 (00:41 +0000)
Makefile patch | blob | history

diff --git a/Makefile b/Makefile
index 7baa46530b534d75f568934fd5b4fc24524e9c9c..fcb8127ee8c8755e9e30b3eb841b6a2a33512b4d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -39,7 +39,7 @@ SIM_MAIN_BRAM=false
 #SIM_MAIN_BRAM=false
 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 
-FPGA_TARGET ?= VERILATOR
+FPGA_TARGET ?= verilator
 
 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true