machxo2: Switch to LUT4 sim model which propagates less undefined/don't care values.

diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v
index c6d70a055054736931b9b478b54ec212694dce28..161ddfe2ea3250ea273d18d0f9d9ffad14c069e5 100644 (file)
--- a/techlibs/machxo2/cells_sim.v
+++ b/techlibs/machxo2/cells_sim.v
@@ -4,17 +4,11 @@ module LUT4 #(
        input A, B, C, D,
        output Z
 );
-       wire [3:0] I;
-       wire [3:0] I_pd;
-
-       genvar ii;
-       generate
-               for (ii = 0; ii < 4; ii = ii + 1'b1)
-                       assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
-       endgenerate
-
-       assign I = {D, C, B, A};
-       assign Z = INIT[I_pd];
+       // This form of LUT propagates as few x's as possible.
+       wire [7:0] s3 = D ?     INIT[15:8] :     INIT[7:0];
+       wire [3:0] s2 = C ?       s3[ 7:4] :       s3[3:0];
+       wire [1:0] s1 = B ?       s2[ 3:2] :       s2[1:0];
+       assign Z =      A ?          s1[1] :         s1[0];
 endmodule
 
 module FACADE_FF #(

diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys
index 0cfc365bd16d18543a4e44279d5f59785af2658f..6c8aa857c0fffde9e85137ec427254901e3edc38 100644 (file)
--- a/tests/arch/machxo2/mux.ys
+++ b/tests/arch/machxo2/mux.ys
@@ -35,6 +35,6 @@ proc
 equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux16 # Constrain all select calls below inside the top module
-select -assert-count 12 t:LUT4
+select -assert-count 11 t:LUT4
 
 select -assert-none t:LUT4 t:FACADE_IO %% t:* %D