[libre-riscv-dev] [Bug 340] New: formal proof of POWER9 SHIFTROT pipeline needed
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Fri, 22 May 2020 20:28:41 +0000 (20:28 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Fri, 22 May 2020 20:28:42 +0000 (21:28 +0100)
cc/5e6eceb57b7cf27a57c96aa498924137071a01 [new file with mode: 0644]

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+Date: Fri, 22 May 2020 20:28:41 +0000
+X-Bugzilla-Reason: CC
+X-Bugzilla-Type: new
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Formal Verification
+X-Bugzilla-Version: unspecified
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Subject: [libre-riscv-dev] [Bug 340] New: formal proof of POWER9 SHIFTROT
+ pipeline needed
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