--- /dev/null
+package ifc_sync;
+
+ import Clocks::*;
+ import GetPut::*;
+
+ (*always_ready,always_enabled*)
+ interface Ifc_sync#(type a);
+ (*always_ready,always_enabled*)
+ interface Put#(a) put;
+ (*always_ready,always_enabled*)
+ interface Get#(a) get;
+ endinterface
+ module mksyncconnection#(Clock putclock, Reset putreset,
+ Clock getclock, Reset getreset)(Ifc_sync#(a))
+ provisos(Bits#(a, a__));
+ CrossingReg#(a) null_wire<- mkNullCrossingReg(getclock,?,
+ clocked_by putclock,
+ reset_by putreset);
+ // ReadOnly#(Bit#(a)) null_wire <- mkNullCrossingWire(getclock,
+// from_put, clocked_by getclock,
+// reset_by getreset);
+ interface put = interface Put
+ method Action put(a in);
+ null_wire<= in;
+ endmethod
+ endinterface;
+ interface get = interface Get
+ method ActionValue#(a) get();
+ return null_wire.crossed;
+ endmethod
+ endinterface;
+ endmodule
+
+endpackage
+
*/
package BootRom;
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import BRAMCore :: *;
import DReg::*;
import Semi_FIFOF :: *;
/*======================== */
/*==== Project imports ====*/
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
/*=========================*/
interface Ifc_clint;
import ConfigReg :: *;
`define Burst_length_bits 8
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
`define verbose
// ================================================================
// DMA requests and responses parameters
import Clocks :: * ;
import DReg ::*;
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
`define Num_DMA_Channels 7
import RegFile::*;
import Clocks :: * ;
import DReg ::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
typedef 2 Num_Masters;
typedef 3 Num_Slaves;
// FlexBus External Signals
// AD inout bus separate for now in BSV
+ (* always_ready *)
interface Get#(Bit#(32)) m_AD; // out
+ (* always_ready *)
interface Put#(Bit#(32)) m_din; // in
+ (* always_ready *)
interface Get#(Bit#(32)) m_OE32n; // out 32-bits, same as OEn
+ (* always_ready *)
interface Get#(Bit#(1)) m_R_Wn; // out
+ (* always_ready *)
interface Get#(Bit#(2)) m_TSIZ; // out
+ (* always_ready *)
interface Get#(Bit#(6)) m_FBCSn; // out
+ (* always_ready *)
interface Get#(Bit#(4)) m_BWEn; // out
+ (* always_ready *)
interface Get#(Bit#(1)) m_TBSTn; // out
+ (* always_ready *)
interface Get#(Bit#(1)) m_OEn; // out
+ (* always_ready *)
interface Get#(Bit#(1)) m_ALE; // out
+ (* always_ready *)
interface Put#(Bit#(1)) m_tAn; // in
endinterface: FlexBus_Master_IFC
interface GPIO#(numeric type ionum);
interface GPIO_config#(ionum) pad_config;
interface GPIO_func#(ionum) func;
- interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
endinterface
module mkgpio(GPIO#(ionum_));
Vector#(ionum_,ConfigReg#(Bit#(1))) pwrupzhl_reg <-replicateM(mkConfigReg(0));
Vector#(ionum_,ConfigReg#(Bit#(1))) pwrup_pull_en_reg <-replicateM(mkConfigReg(0));
- AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
+ AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
rule rl_wr_respond;
// Get the wr request
let aw <- pop_o (s_xactor.o_wr_addr);
--- /dev/null
+### Makefile for the cclass project
+
+TOP_MODULE:=mkjtagdtm
+TOP_FILE:=jtagdtm.bsv
+TOP_DIR:=./
+WORKING_DIR := $(shell pwd)
+
+BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./bsv_lib/
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4
+BSVINCDIR:= $(BSVINCDIR):../../lib
+BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite
+BSVINCDIR:= $(BSVINCDIR):./test
+
+default: gen_verilog
+
+check-blue:
+ @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi;
+
+###### Setting the variables for bluespec compile #$############################
+BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules
+BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires
+VERILOGDIR:=./verilog/
+BSVBUILDDIR:=./bsv_build/
+BSVOUTDIR:=./bin
+################################################################################
+
+########## BSIM COMPILE, LINK AND SIMULATE TARGETS ##########################
+.PHONY: check-restore
+check-restore:
+ @if [ "$(define_macros)" != "$(old_define_macros)" ]; then make clean ; fi;
+
+.PHONY: gen_verilog
+gen_verilog: check-restore check-blue
+ @echo Compiling mkTbSoc in Verilog for simulations ...
+ @mkdir -p $(BSVBUILDDIR);
+ @mkdir -p $(VERILOGDIR);
+ bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log
+ @echo Compilation finished
+
+#############################################################################
+
+.PHONY: clean
+clean:
+ rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl*
+ rm -rf verilog obj_dir bsv_src
/*====== Package imports ======= */
import Clocks::*;
import ConcatReg::*;
+ import GetPut::*;
import FIFO::*;
import FIFOF::*;
import SpecialFIFOs::*;
import DReg::*;
/*======= Project imports ===== */
`include "jtagdefines.bsv"
- import defined_types::*;
+ //import defined_types::*;
/*============================== */
interface Ifc_jtagdtm;
method Bit#(1) scan_shift_en;
/*======== JTAG input pins ===== */
(*always_enabled,always_ready*)
- method Action tms_i(Bit#(1) tms);
+ interface Put#(Bit#(1)) tms;
(*always_enabled,always_ready*)
- method Action tdi_i(Bit#(1) tdi);
+ interface Put#(Bit#(1)) tdi;
/*==== inputs from Sub-modules === */
method Action debug_tdi_i(Bit#(1) debug_tdi);
/*======= JTAG Output Pins ====== */
(*always_enabled,always_ready*)
- method Bit#(1) tdo;
- method Bit#(1) tdo_oe;
+ interface Get#(Bit#(1)) tdo;
+ (*always_enabled,always_ready*)
+ interface Get#(Bit#(1)) tck;
+
/*======== TAP States ============= */
method Bit#(1) shift_dr;
method Bit#(1) pause_dr;
scan_out_5_sr<=scan_out_5;
endmethod
/*======== JTAG input pins ===== */
- method Action tms_i(Bit#(1) tms);
- wr_tms<=tms;
- endmethod
- method Action tdi_i(Bit#(1) tdi);
- wr_tdi<=tdi;
- endmethod
+
+ interface tms = interface Put
+ method Action put(Bit#(1) in);
+ wr_tms<=in;
+ endmethod
+ endinterface;
+
+ interface tdi = interface Put
+ method Action put(Bit#(1) in);
+ wr_tdi<=in;
+ endmethod
+ endinterface;
+
/*============================= */
method Action debug_tdi_i(Bit#(1) debug_tdi);
wr_debug_tdi<=debug_tdi;
method bscan_in = bs_sr;
method scan_shift_en = wr_scan_shift_en[1];
/*======= JTAG Output Pins ====== */
- method tdo = crossed_output_tdo;
+ interface tck = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
+ endmethod
+ endinterface;
+
+ interface tdo = interface Get
+ method ActionValue#(Bit#(1)) get;
+ return crossed_output_tdo;
+ endmethod
+ endinterface;
+
method debug_tdo = wr_tdi;
- method Bit#(1) tdo_oe = ((tapstate == ShiftIR) || (tapstate == ShiftDR))?1:0;
method Action response_from_dm(Bit#(34) responsedm) if(response_from_DM.notFull);
if(capture_repsonse_from_dm)
response_from_DM.enq(responsedm);
--- /dev/null
+`define ADDR 32
+`define PADDR 32
+`define DATA 64
+`define Reg_width 64
+`define USERSPACE 0
+
+// TODO: work out if these are needed
+`define PWM_AXI4Lite
+`define PRFDEPTH 6
+`define VADDR 39
+`define DCACHE_BLOCK_SIZE 4
+`define DCACHE_WORD_SIZE 8
+`define PERFMONITORS 64
+`define DCACHE_WAYS 4
+`define DCACHE_TAG_BITS 20 // tag_bits = 52
+`define PLIC
+ `define PLICBase 'h0c000000
+ `define PLICEnd 'h10000000
+`define INTERRUPT_PINS 64
+
+`define BAUD_RATE 130
+`ifdef simulate
+ `define BAUD_RATE 5 //130 //
+`endif
interface MUX#(numeric type ionum);
interface MUX_config#(ionum) mux_config;
- interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USERSPACE) axi_slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR,`DATA,`USERSPACE) axi_slave;
endinterface
// (*synthesize*)
module mkmux(MUX#(ionum_));
Vector#(ionum_,ConfigReg#(Bit#(2))) muxer_reg <-replicateM(mkConfigReg(0));
- AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
+ AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `DATA, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
let ionum=valueOf(ionum_);
rule rl_wr_respond;
// Get the wr request
import AXI4_Types::*;
interface Ifc_rgbttl_dummy;
- interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
- interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
- interface Get#(Bit#(1)) de;
- interface Get#(Bit#(1)) ck;
- interface Get#(Bit#(1)) vs;
- interface Get#(Bit#(1)) hs;
- interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
+ interface AXI4_Master_IFC#(`PADDR, `DATA, `USERSPACE) master;
+ interface AXI4_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
+ (* always_ready *) interface Get#(Bit#(1)) de;
+ (* always_ready *) interface Get#(Bit#(1)) ck;
+ (* always_ready *) interface Get#(Bit#(1)) vs;
+ (* always_ready *) interface Get#(Bit#(1)) hs;
+ (* always_ready *) interface Get#(Bit#(`RGBTTL_WIDTH)) data_out;
endinterface
(*synthesize*)
module mkrgbttl_dummy(Ifc_rgbttl_dummy);
- AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Slave_Xactor();
- AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Master_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
m_xactor<-mkAXI4_Master_Xactor();
Reg#(Bit#(1)) rg_de <- mkReg(0);
import AXI4_Lite_Types::*;
interface Ifc_sdcard_dummy;
- interface AXI4_Lite_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;
+ interface AXI4_Lite_Slave_IFC#(`PADDR, `DATA, `USERSPACE) slave;
interface Get#(Bit#(1)) cmd;
interface Get#(Bit#(1)) clk;
interface Get#(Bit#(`SDBUSWIDTH)) out;
(*synthesize*)
module mksdcard_dummy(Ifc_sdcard_dummy);
- AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+ AXI4_Lite_Slave_Xactor_IFC#(`PADDR,`DATA, `USERSPACE)
s_xactor<-mkAXI4_Lite_Slave_Xactor();
Reg#(Bit#(1)) rg_cmd <- mkReg(0);
---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
*/
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
`define DELAY 250
`define SDR_RFSH_TIMER_W 12
`define SDR_RFSH_ROW_CNT_W 3
import AXI4_Fabric :: *;
import bsvmksdram_model_wrapper :: *;
import Connectable :: *;
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
`define DELAY 10200
import sdr_top :: *;
import tb_bsv_wrapper :: *;
import Connectable :: *;
-`include "defined_parameters.bsv"
+`include "instance_defines.bsv"
typedef 1 Num_Masters;
package TCM;
/*====== Porject imports ====*/
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import Semi_FIFOF :: *;
import AXI4_Types :: *;
import AXI4_Fabric :: *;
(QUART_AXI4_Lite_Ifc);
Uart16550_AXI4_Lite_Ifc uart <- mkUart16550(core_clock, core_reset);
- //uart.pin_dsr_sync <= in;
- //uart.pin_ri_sync <= in;
- //uart.pin_dcd_sync <= in;
+
+ // ok set up CDC and dsr to 1, and Ring to 0. and otherwise ignore them
rule rl_put;
- Bit#(1) v1 = 1;
- Bit#(1) v0 = 1;
- uart.coe_rs232.dsr_in.put(1);
-
- uart.coe_rs232.dcd_in.put(1);
- uart.coe_rs232.ri_in.put(0);
+ uart.coe_rs232.dsr_in.put(1);
+ uart.coe_rs232.dcd_in.put(1);
+ uart.coe_rs232.ri_in.put(0);
endrule
-
+ // deliberately drop (ignore) this value
rule rl_get;
- let temp2 <- uart.coe_rs232.dtr_out.get;
+ let temp2 <- uart.coe_rs232.dtr_out.get;
endrule
interface out = interface QUART_out
package Memory_vme_16;
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import BRAMCore :: *;
// import TriState ::*;
// import DReg::*;
package Memory_vme_32;
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import BRAMCore :: *;
`include "vme_parameters.bsv"
package Memory_vme_8;
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import BRAMCore :: *;
/*========= Project imports ======== */
`include "vme_parameters.bsv"
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import defined_types ::*;
import FIFOF ::*;
import vme_master :: *;
import AXI4_Types::*;
import AXI4_Fabric::*;
`include "defines.bsv"
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
import defined_types::*;
import core :: *;
/*========================= */
package MemoryMap;
/*=== Project imports ==== */
import defined_types::*;
- `include "defined_parameters.bsv"
+ `include "instance_defines.bsv"
/*========================= */