core/cpu/CPUNone: set endianness to little.

diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py
index 47f4519f002b927d6ad098992a05e4aa39344fd0..ebb36086c86a7e028e67735d928ed012a2c2048e 100644 (file)
--- a/litex/soc/cores/cpu/__init__.py
+++ b/litex/soc/cores/cpu/__init__.py
@@ -26,6 +26,7 @@ class CPU(Module):
 class CPUNone(CPU):
     variants             = ["standard"]
     data_width           = 32
+    endianness           = "little"
     reset_address        = 0x00000000
     io_regions           = {0x00000000: 0x100000000} # origin, length
     periph_buses         = []