disable hyperram for now (under investigation)

diff --git a/src/ls2.py b/src/ls2.py
index 05966db23deb9204555105909fc7870d35ee4920..4f63cc33ef89b1bae4a92e8ee59f763559228f5d 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -467,7 +467,9 @@ class DDR3SoC(SoC, Elaboratable):
 
         # add hyperram module
         if hasattr(self, "hyperram"):
-            m.submodules.hyperram = self.hyperram
+            m.submodules.hyperram = hyperram = self.hyperram
+            # grrr, same problem with hyperram: not WB4-pipe compliant
+            comb += hyperram.bus.stall.eq(hyperram.bus.cyc & ~hyperram.bus.ack)
 
         # add blinky lights so we know FPGA is alive
         if platform is not None:
@@ -623,6 +625,9 @@ if __name__ == "__main__":
     else:
         hyperram_pins = HyperRAMPads()
 
+    # broken at the moment
+    hyperram_pins = None
+
     # set up the SOC
     soc = DDR3SoC(fpga=fpga, dram_cls=dram_cls,
                   # check microwatt_soc.h for these