self.add_csr()
def add_csr(self):
- self._base = CSRStorage(32)
+ self._base = CSRStorage(64)
self._length = CSRStorage(32)
self._enable = CSRStorage()
self._done = CSRStatus()
self._sink = self.sink
self.sink = stream.Endpoint([("data", self.bus.data_width)])
- self._base = CSRStorage(32)
+ self._base = CSRStorage(64)
self._length = CSRStorage(32)
self._enable = CSRStorage()
self._done = CSRStatus()
{
/* Initialize DMA Writer */
sdblock2mem_dma_enable_write(0);
- sdblock2mem_dma_base_write((uint32_t) buf);
+ sdblock2mem_dma_base_write((uint64_t) buf);
sdblock2mem_dma_length_write(512*count);
sdblock2mem_dma_enable_write(1);
while (count--) {
/* Initialize DMA Reader */
sdmem2block_dma_enable_write(0);
- sdmem2block_dma_base_write((uint32_t) buf);
+ sdmem2block_dma_base_write((uint64_t) buf);
sdmem2block_dma_length_write(512);
sdmem2block_dma_enable_write(1);