arch-power: Add fixed-point logical extend sign instructions

This adds the following logical instructions:
  * Extend Sign Word (extsw[.])

Change-Id: I610e84c2361b99b00ceef2170ede5b6dee8ec21b
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

diff --git a/src/arch/power/insts/integer.cc b/src/arch/power/insts/integer.cc
index d3672472c694553b019b1bc40a5d7ef66f7d34c6..f87afa2821af34f65c0723dd3d5ffc02ed986a6e 100644 (file)
--- a/src/arch/power/insts/integer.cc
+++ b/src/arch/power/insts/integer.cc
@@ -292,6 +292,7 @@ IntLogicOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
         printSecondSrc = false;
     } else if (!myMnemonic.compare("extsb") ||
                !myMnemonic.compare("extsh") ||
+               !myMnemonic.compare("extsw") ||
                !myMnemonic.compare("cntlzw")) {
         printSecondSrc = false;
     }

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index d80846f99c630ce4c4f963f831dc371ab26f2c7d..6390017af3bde4f33821d926b95faca859715cfa 100644 (file)
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -513,6 +513,7 @@ decode PO default Unknown::unknown() {
             412: orc({{ Ra = Rs | ~Rb; }}, true);
             954: extsb({{ Ra = Rs_sb; }}, true);
             922: extsh({{ Ra = Rs_sh; }}, true);
+            986: extsw({{ Ra = Rs_sw; }}, true);
             26: cntlzw({{ Ra = findLeadingZeros(Rs_uw); }}, true);
 
             508: cmpb({{