class ECPIX5Platform(LatticeECP5Platform):
- device = "LFE5UM5G-85F"
- package = "BG554"
- speed = "8"
+ device = "LFE5UM5G-85F"
+ package = "BG554"
+ speed = "8"
default_clk = "clk100"
default_rst = "rst"
- resources = [
+ resources = [
Resource("rst", 0, PinsN("AB1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
- Resource("clk100", 0, Pins("K23", dir="i"), Clock(100e6), Attrs(IO_TYPE="LVCMOS33")),
-
- RGBLEDResource(0, r="U21", g="W21", b="T24", attrs=Attrs(IO_TYPE="LVCMOS33")),
- RGBLEDResource(1, r="T23", g="R21", b="T22", attrs=Attrs(IO_TYPE="LVCMOS33")),
- RGBLEDResource(2, r="P21", g="R23", b="P22", attrs=Attrs(IO_TYPE="LVCMOS33")),
- RGBLEDResource(3, r="K21", g="K24", b="M21", attrs=Attrs(IO_TYPE="LVCMOS33")),
+ Resource("clk100", 0, Pins("K23", dir="i"),
+ Clock(100e6), Attrs(IO_TYPE="LVCMOS33")),
+
+ RGBLEDResource(0, r="U21", g="W21", b="T24",
+ attrs=Attrs(IO_TYPE="LVCMOS33")),
+ RGBLEDResource(1, r="T23", g="R21", b="T22",
+ attrs=Attrs(IO_TYPE="LVCMOS33")),
+ RGBLEDResource(2, r="P21", g="R23", b="P22",
+ attrs=Attrs(IO_TYPE="LVCMOS33")),
+ RGBLEDResource(3, r="K21", g="K24", b="M21",
+ attrs=Attrs(IO_TYPE="LVCMOS33")),
UARTResource(0,
- rx="R26", tx="R24",
- attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
- ),
+ rx="R26", tx="R24",
+ attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
+ ),
*SPIFlashResources(0,
- cs="AA2", clk="AE3", miso="AE2", mosi="AD2", wp="AF2", hold="AE1",
- attrs=Attrs(IO_TYPE="LVCMOS33")
- ),
+ cs="AA2", clk="AE3", miso="AE2", mosi="AD2", wp="AF2", hold="AE1",
+ attrs=Attrs(IO_TYPE="LVCMOS33")
+ ),
Resource("eth_rgmii", 0,
- Subsignal("rst", PinsN("C13", dir="o")),
- Subsignal("mdio", Pins("A13", dir="io")),
- Subsignal("mdc", Pins("C11", dir="o")),
- Subsignal("tx_clk", Pins("A12", dir="o")),
- Subsignal("tx_ctrl", Pins("C9", dir="o")),
- Subsignal("tx_data", Pins("D8 C8 B8 A8", dir="o")),
- Subsignal("rx_clk", Pins("E11", dir="i")),
- Subsignal("rx_ctrl", Pins("A11", dir="i")),
- Subsignal("rx_data", Pins("B11 A10 B10 A9", dir="i")),
- Attrs(IO_TYPE="LVCMOS33")
- ),
- Resource("eth_int", 0, PinsN("B13", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
+ Subsignal("rst", PinsN("C13", dir="o")),
+ Subsignal("mdio", Pins("A13", dir="io")),
+ Subsignal("mdc", Pins("C11", dir="o")),
+ Subsignal("tx_clk", Pins("A12", dir="o")),
+ Subsignal("tx_ctrl", Pins("C9", dir="o")),
+ Subsignal("tx_data", Pins("D8 C8 B8 A8", dir="o")),
+ Subsignal("rx_clk", Pins("E11", dir="i")),
+ Subsignal("rx_ctrl", Pins("A11", dir="i")),
+ Subsignal("rx_data", Pins("B11 A10 B10 A9", dir="i")),
+ Attrs(IO_TYPE="LVCMOS33")
+ ),
+ Resource("eth_int", 0, PinsN("B13", dir="i"),
+ Attrs(IO_TYPE="LVCMOS33")),
*SDCardResources(0,
- clk="P24", cmd="M24", dat0="N26", dat1="N25", dat2="N23", dat3="N21", cd="L22",
- # TODO
- # clk_fb="P25", cmd_dir="M23", dat0_dir="N24", dat123_dir="P26",
- attrs=Attrs(IO_TYPE="LVCMOS33"),
- ),
+ clk="P24", cmd="M24", dat0="N26", dat1="N25", dat2="N23", dat3="N21", cd="L22",
+ # TODO
+ # clk_fb="P25", cmd_dir="M23", dat0_dir="N24", dat123_dir="P26",
+ attrs=Attrs(IO_TYPE="LVCMOS33"),
+ ),
# ERROR: cannot place differential IO at location PIOB
# if we choose to use DiffPairs
Resource("ddr3", 0,
- Subsignal("clk", Pins("H3", dir="o")),
- #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
- Subsignal("cke", Pins("P1", dir="o")),
- Subsignal("we_n", Pins("R3", dir="o")),
- Subsignal("ras_n", Pins("T3", dir="o")),
- Subsignal("cas_n", Pins("P2", dir="o")),
- Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
- Subsignal("ba", Pins("U6 N3 N4", dir="o")),
- #Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
- Subsignal("dqs", Pins("V4 V1", dir="io"), Attrs(IO_TYPE="SSTL135D_I", TERMINATION="OFF", DIFFRESISTOR="100")),
- Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")),
- Subsignal("dm", Pins("J4 H5", dir="o")),
- Subsignal("odt", Pins("P3", dir="o")),
- Attrs(IO_TYPE="SSTL135_I")
- ),
+ Subsignal("clk", Pins("H3", dir="o")),
+ #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
+ Subsignal("cke", Pins("P1", dir="o")),
+ Subsignal("we_n", Pins("R3", dir="o")),
+ Subsignal("ras_n", Pins("T3", dir="o")),
+ Subsignal("cas_n", Pins("P2", dir="o")),
+ Subsignal("a", Pins(
+ "T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
+ Subsignal("ba", Pins("U6 N3 N4", dir="o")),
+ #Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
+ Subsignal("dqs", Pins("V4 V1", dir="io"), Attrs(
+ IO_TYPE="SSTL135D_I", TERMINATION="OFF", DIFFRESISTOR="100")),
+ Subsignal("dq", Pins(
+ "T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")),
+ Subsignal("dm", Pins("J4 H5", dir="o")),
+ Subsignal("odt", Pins("P3", dir="o")),
+ Attrs(IO_TYPE="SSTL135_I")
+ ),
Resource("hdmi", 0,
- Subsignal("rst", PinsN("N6", dir="o")),
- Subsignal("scl", Pins("C17", dir="io")),
- Subsignal("sda", Pins("E17", dir="io")),
- Subsignal("pclk", Pins("C1", dir="o")),
- Subsignal("vsync", Pins("A4", dir="o")),
- Subsignal("hsync", Pins("B4", dir="o")),
- Subsignal("de", Pins("A3", dir="o")),
- Subsignal("d",
- Subsignal("b", Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3", dir="o")),
- Subsignal("g", Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6", dir="o")),
- Subsignal("r", Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4", dir="o")),
- ),
- Subsignal("mclk", Pins("E19", dir="o")),
- Subsignal("sck", Pins("D6", dir="o")),
- Subsignal("ws", Pins("C6", dir="o")),
- Subsignal("i2s", Pins("A6 B6 A5 C5", dir="o")),
- Subsignal("int", PinsN("C4", dir="i")),
- Attrs(IO_TYPE="LVTTL33")
- ),
+ Subsignal("rst", PinsN("N6", dir="o")),
+ Subsignal("scl", Pins("C17", dir="io")),
+ Subsignal("sda", Pins("E17", dir="io")),
+ Subsignal("pclk", Pins("C1", dir="o")),
+ Subsignal("vsync", Pins("A4", dir="o")),
+ Subsignal("hsync", Pins("B4", dir="o")),
+ Subsignal("de", Pins("A3", dir="o")),
+ Subsignal("d",
+ Subsignal(
+ "b", Pins("AD25 AC26 AB24 AB25 B3 C3 D3 B1 C2 D2 D1 E3", dir="o")),
+ Subsignal(
+ "g", Pins("AA23 AA22 AA24 AA25 E1 F2 F1 D17 D16 E16 J6 H6", dir="o")),
+ Subsignal(
+ "r", Pins("AD26 AE25 AF25 AE26 E10 D11 D10 C10 D9 E8 H5 J4", dir="o")),
+ ),
+ Subsignal("mclk", Pins("E19", dir="o")),
+ Subsignal("sck", Pins("D6", dir="o")),
+ Subsignal("ws", Pins("C6", dir="o")),
+ Subsignal("i2s", Pins("A6 B6 A5 C5", dir="o")),
+ Subsignal("int", PinsN("C4", dir="i")),
+ Attrs(IO_TYPE="LVTTL33")
+ ),
Resource("sata", 0,
- Subsignal("tx", DiffPairs("AD16", "AD17", dir="o")),
- Subsignal("rx", DiffPairs("AF15", "AF16", dir="i")),
- Attrs(IO_TYPE="LVDS")
- ),
+ Subsignal("tx", DiffPairs("AD16", "AD17", dir="o")),
+ Subsignal("rx", DiffPairs("AF15", "AF16", dir="i")),
+ Attrs(IO_TYPE="LVDS")
+ ),
Resource("ulpi", 0,
- Subsignal("rst", Pins("E23", dir="o")),
- Subsignal("clk", Pins("H24", dir="i")),
- Subsignal("dir", Pins("F22", dir="i")),
- Subsignal("nxt", Pins("F23", dir="i")),
- Subsignal("stp", Pins("H23", dir="o")),
- Subsignal("data", Pins("M26 L25 L26 K25 K26 J23 J26 H25", dir="io")),
- Attrs(IO_TYPE="LVCMOS33")
- ),
+ Subsignal("rst", Pins("E23", dir="o")),
+ Subsignal("clk", Pins("H24", dir="i")),
+ Subsignal("dir", Pins("F22", dir="i")),
+ Subsignal("nxt", Pins("F23", dir="i")),
+ Subsignal("stp", Pins("H23", dir="o")),
+ Subsignal("data", Pins(
+ "M26 L25 L26 K25 K26 J23 J26 H25", dir="io")),
+ Attrs(IO_TYPE="LVCMOS33")
+ ),
Resource("usbc_cfg", 0,
- Subsignal("scl", Pins("D24", dir="io")),
- Subsignal("sda", Pins("C24", dir="io")),
- Subsignal("dir", Pins("B23", dir="i")),
- Subsignal("id", Pins("D23", dir="i")),
- Subsignal("int", PinsN("B24", dir="i")),
- Attrs(IO_TYPE="LVCMOS33")
- ),
+ Subsignal("scl", Pins("D24", dir="io")),
+ Subsignal("sda", Pins("C24", dir="io")),
+ Subsignal("dir", Pins("B23", dir="i")),
+ Subsignal("id", Pins("D23", dir="i")),
+ Subsignal("int", PinsN("B24", dir="i")),
+ Attrs(IO_TYPE="LVCMOS33")
+ ),
Resource("usbc_mux", 0,
- Subsignal("en", Pins("C23", dir="oe")),
- Subsignal("amsel", Pins("B26", dir="oe")),
- Subsignal("pol", Pins("D26", dir="o")),
- Subsignal("lna", DiffPairs( "AF9", "AF10", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
- Subsignal("lnb", DiffPairs("AD10", "AD11", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
- Subsignal("lnc", DiffPairs( "AD7", "AD8", dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
- Subsignal("lnd", DiffPairs( "AF6", "AF7", dir="i"), Attrs(IO_TYPE="LVCMOS18D")),
- Attrs(IO_TYPE="LVCMOS33")
- ),
+ Subsignal("en", Pins("C23", dir="oe")),
+ Subsignal("amsel", Pins("B26", dir="oe")),
+ Subsignal("pol", Pins("D26", dir="o")),
+ Subsignal("lna", DiffPairs("AF9", "AF10", dir="i"),
+ Attrs(IO_TYPE="LVCMOS18D")),
+ Subsignal("lnb", DiffPairs("AD10", "AD11",
+ dir="o"), Attrs(IO_TYPE="LVCMOS18D")),
+ Subsignal("lnc", DiffPairs("AD7", "AD8", dir="o"),
+ Attrs(IO_TYPE="LVCMOS18D")),
+ Subsignal("lnd", DiffPairs("AF6", "AF7", dir="i"),
+ Attrs(IO_TYPE="LVCMOS18D")),
+ Attrs(IO_TYPE="LVCMOS33")
+ ),
]
- connectors = [
+ connectors = [
Connector("pmod", 0, "T25 U25 U24 V24 - - T26 U26 V26 W26 - -"),
Connector("pmod", 1, "U23 V23 U22 V21 - - W25 W24 W23 W22 - -"),
Connector("pmod", 2, "J24 H22 E21 D18 - - K22 J21 H21 D22 - -"),
with products.extract("{}-openocd.cfg".format(name), "{}.svf".format(name)) \
as (config_filename, vector_filename):
subprocess.check_call([openocd,
- "-f", config_filename,
- "-c", "transport select jtag; init; svf -quiet {}; exit".format(vector_filename)
- ])
+ "-f", config_filename,
+ "-c", "transport select jtag; init; svf -quiet {}; exit".format(
+ vector_filename)
+ ])
# if __name__ == "__main__":
from customecpix5 import ECPIX5Platform
+
class PLL(Elaboratable):
- def __init__(self, clkin, clksel=Signal(shape=2, reset=2), clkout1=Signal(), clkout2=Signal(), clkout3=Signal(), clkout4=Signal(), lock=Signal(), CLKI_DIV=1, CLKFB_DIV=1, CLK1_DIV=3, CLK2_DIV=4, CLK3_DIV=5, CLK4_DIV=6):
- self.clkin = clkin
- self.clkout1 = clkout1
- self.clkout2 = clkout2
- self.clkout3 = clkout3
- self.clkout4 = clkout4
- self.clksel = clksel
- self.lock = lock
- self.CLKI_DIV = CLKI_DIV
- self.CLKFB_DIV = CLKFB_DIV
- self.CLKOP_DIV = CLK1_DIV
- self.CLKOS_DIV = CLK2_DIV
- self.CLKOS2_DIV = CLK3_DIV
- self.CLKOS3_DIV = CLK4_DIV
- self.ports = [
- self.clkin,
- self.clkout1,
- self.clkout2,
- self.clkout3,
- self.clkout4,
- self.clksel,
- self.lock,
- ]
-
- def elaborate(self, platform):
- clkfb = Signal()
- pll = Instance("EHXPLLL",
- p_PLLRST_ENA='DISABLED',
- p_INTFB_WAKE='DISABLED',
- p_STDBY_ENABLE='DISABLED',
- p_CLKOP_FPHASE=0,
- p_CLKOP_CPHASE=11,
- p_OUTDIVIDER_MUXA='DIVA',
- p_CLKOP_ENABLE='ENABLED',
- p_CLKOP_DIV=self.CLKOP_DIV, #Max 948 MHz at OP=79 FB=1 I=1 F_in=12 MHz, Min 30 MHz (28 MHz locks sometimes, lock LED blinks) Hmm... /3*82/25
- p_CLKOS_DIV=self.CLKOS_DIV,
- p_CLKOS2_DIV=self.CLKOS2_DIV,
- p_CLKOS3_DIV=self.CLKOS3_DIV,
- p_CLKFB_DIV=self.CLKFB_DIV, #25
- p_CLKI_DIV=self.CLKI_DIV, #6
- p_FEEDBK_PATH='USERCLOCK',
- i_CLKI=self.clkin,
- i_CLKFB=clkfb,
- i_RST=0,
- i_STDBY=0,
- i_PHASESEL0=0,
- i_PHASESEL1=0,
- i_PHASEDIR=0,
- i_PHASESTEP=0,
- i_PLLWAKESYNC=0,
- i_ENCLKOP=0,
- i_ENCLKOS=0,
- i_ENCLKOS2=0,
- i_ENCLKOS3=0,
- o_CLKOP=self.clkout1,
- o_CLKOS=self.clkout2,
- o_CLKOS2=self.clkout3,
- o_CLKOS3=self.clkout4,
- o_LOCK=self.lock,
- #o_LOCK=pll_lock
- )
- m = Module()
- m.submodules += pll
- with m.If(self.clksel == 0):
- m.d.comb += clkfb.eq(self.clkout1)
- with m.Elif(self.clksel == 1):
- m.d.comb += clkfb.eq(self.clkout2)
- with m.Elif(self.clksel == 2):
- m.d.comb += clkfb.eq(self.clkout3)
- with m.Else():
- m.d.comb += clkfb.eq(self.clkout4)
- return m
+ def __init__(self, clkin, clksel=Signal(shape=2, reset=2), clkout1=Signal(), clkout2=Signal(), clkout3=Signal(), clkout4=Signal(), lock=Signal(), CLKI_DIV=1, CLKFB_DIV=1, CLK1_DIV=3, CLK2_DIV=4, CLK3_DIV=5, CLK4_DIV=6):
+ self.clkin = clkin
+ self.clkout1 = clkout1
+ self.clkout2 = clkout2
+ self.clkout3 = clkout3
+ self.clkout4 = clkout4
+ self.clksel = clksel
+ self.lock = lock
+ self.CLKI_DIV = CLKI_DIV
+ self.CLKFB_DIV = CLKFB_DIV
+ self.CLKOP_DIV = CLK1_DIV
+ self.CLKOS_DIV = CLK2_DIV
+ self.CLKOS2_DIV = CLK3_DIV
+ self.CLKOS3_DIV = CLK4_DIV
+ self.ports = [
+ self.clkin,
+ self.clkout1,
+ self.clkout2,
+ self.clkout3,
+ self.clkout4,
+ self.clksel,
+ self.lock,
+ ]
+
+ def elaborate(self, platform):
+ clkfb = Signal()
+ pll = Instance("EHXPLLL",
+ p_PLLRST_ENA='DISABLED',
+ p_INTFB_WAKE='DISABLED',
+ p_STDBY_ENABLE='DISABLED',
+ p_CLKOP_FPHASE=0,
+ p_CLKOP_CPHASE=11,
+ p_OUTDIVIDER_MUXA='DIVA',
+ p_CLKOP_ENABLE='ENABLED',
+ # Max 948 MHz at OP=79 FB=1 I=1 F_in=12 MHz, Min 30 MHz (28 MHz locks sometimes, lock LED blinks) Hmm... /3*82/25
+ p_CLKOP_DIV=self.CLKOP_DIV,
+ p_CLKOS_DIV=self.CLKOS_DIV,
+ p_CLKOS2_DIV=self.CLKOS2_DIV,
+ p_CLKOS3_DIV=self.CLKOS3_DIV,
+ p_CLKFB_DIV=self.CLKFB_DIV, # 25
+ p_CLKI_DIV=self.CLKI_DIV, # 6
+ p_FEEDBK_PATH='USERCLOCK',
+ i_CLKI=self.clkin,
+ i_CLKFB=clkfb,
+ i_RST=0,
+ i_STDBY=0,
+ i_PHASESEL0=0,
+ i_PHASESEL1=0,
+ i_PHASEDIR=0,
+ i_PHASESTEP=0,
+ i_PLLWAKESYNC=0,
+ i_ENCLKOP=0,
+ i_ENCLKOS=0,
+ i_ENCLKOS2=0,
+ i_ENCLKOS3=0,
+ o_CLKOP=self.clkout1,
+ o_CLKOS=self.clkout2,
+ o_CLKOS2=self.clkout3,
+ o_CLKOS3=self.clkout4,
+ o_LOCK=self.lock,
+ # o_LOCK=pll_lock
+ )
+ m = Module()
+ m.submodules += pll
+ with m.If(self.clksel == 0):
+ m.d.comb += clkfb.eq(self.clkout1)
+ with m.Elif(self.clksel == 1):
+ m.d.comb += clkfb.eq(self.clkout2)
+ with m.Elif(self.clksel == 2):
+ m.d.comb += clkfb.eq(self.clkout3)
+ with m.Else():
+ m.d.comb += clkfb.eq(self.clkout4)
+ return m
+
class SysClocker(Elaboratable):
- def elaborate(self, platform):
- m = Module()
+ def elaborate(self, platform):
+ m = Module()
+
+ m.submodules.pll = pll = PLL(ClockSignal(
+ "sync"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=2, CLK2_DIV=16)
+ cd_sys2x = ClockDomain("sys2x", local=False)
+ m.d.comb += cd_sys2x.clk.eq(pll.clkout1)
+ m.domains += cd_sys2x
- m.submodules.pll = pll = PLL(ClockSignal("sync"), CLKI_DIV=1, CLKFB_DIV=2, CLK1_DIV=2, CLK2_DIV=16)
- cd_sys2x = ClockDomain("sys2x", local=False)
- m.d.comb += cd_sys2x.clk.eq(pll.clkout1)
- m.domains += cd_sys2x
+ cd_init = ClockDomain("init", local=False)
+ m.d.comb += cd_init.clk.eq(pll.clkout2)
+ m.domains += cd_init
- cd_init = ClockDomain("init", local=False)
- m.d.comb += cd_init.clk.eq(pll.clkout2)
- m.domains += cd_init
+ return m
- return m
class DDR3SoC(CPUSoC, Elaboratable):
- def __init__(self, *, reset_addr, clk_freq,
- rom_addr, rom_size,
- rom2_addr, rom2_size,
- ram_addr, ram_size,
- uart_addr, uart_divisor, uart_pins,
- timer_addr, timer_width,
- ddrphy_addr, dramcore_addr,
- ddr_addr):
- self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
- features={"cti", "bte"})
- self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
- features={"cti", "bte"})
+ def __init__(self, *, reset_addr, clk_freq,
+ rom_addr, rom_size,
+ rom2_addr, rom2_size,
+ ram_addr, ram_size,
+ uart_addr, uart_divisor, uart_pins,
+ timer_addr, timer_width,
+ ddrphy_addr, dramcore_addr,
+ ddr_addr):
+ self._arbiter = wishbone.Arbiter(addr_width=30, data_width=32, granularity=8,
+ features={"cti", "bte"})
+ self._decoder = wishbone.Decoder(addr_width=30, data_width=32, granularity=8,
+ features={"cti", "bte"})
- self.cpu = MinervaCPU(reset_address=reset_addr)
- self._arbiter.add(self.cpu.ibus)
- self._arbiter.add(self.cpu.dbus)
+ self.cpu = MinervaCPU(reset_address=reset_addr)
+ self._arbiter.add(self.cpu.ibus)
+ self._arbiter.add(self.cpu.dbus)
- self.rom = SRAMPeripheral(size=rom_size, writable=False)
- self._decoder.add(self.rom.bus, addr=rom_addr)
+ self.rom = SRAMPeripheral(size=rom_size, writable=False)
+ self._decoder.add(self.rom.bus, addr=rom_addr)
- self.rom2 = SRAMPeripheral(size=rom2_size)
- self._decoder.add(self.rom2.bus, addr=rom2_addr)
+ self.rom2 = SRAMPeripheral(size=rom2_size)
+ self._decoder.add(self.rom2.bus, addr=rom2_addr)
- self.ram = SRAMPeripheral(size=ram_size)
- self._decoder.add(self.ram.bus, addr=ram_addr)
+ self.ram = SRAMPeripheral(size=ram_size)
+ self._decoder.add(self.ram.bus, addr=ram_addr)
- self.uart = AsyncSerialPeripheral(divisor=uart_divisor, pins=uart_pins)
- self._decoder.add(self.uart.bus, addr=uart_addr)
+ self.uart = AsyncSerialPeripheral(divisor=uart_divisor, pins=uart_pins)
+ self._decoder.add(self.uart.bus, addr=uart_addr)
- self.timer = TimerPeripheral(width=timer_width)
- self._decoder.add(self.timer.bus, addr=timer_addr)
+ self.timer = TimerPeripheral(width=timer_width)
+ self._decoder.add(self.timer.bus, addr=timer_addr)
- self.intc = GenericInterruptController(width=len(self.cpu.ip))
- self.intc.add_irq(self.timer.irq, 0)
- self.intc.add_irq(self.uart .irq, 1)
+ self.intc = GenericInterruptController(width=len(self.cpu.ip))
+ self.intc.add_irq(self.timer.irq, 0)
+ self.intc.add_irq(self.uart .irq, 1)
- self.ddrphy = ECP5DDRPHY(platform.request("ddr3", 0))
- self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
+ self.ddrphy = ECP5DDRPHY(platform.request("ddr3", 0))
+ self._decoder.add(self.ddrphy.bus, addr=ddrphy_addr)
- ddrmodule = MT41K256M16(clk_freq, "1:4")
+ ddrmodule = MT41K256M16(clk_freq, "1:4")
- self.dramcore = gramCore(
- phy = self.ddrphy,
- geom_settings = ddrmodule.geom_settings,
- timing_settings = ddrmodule.timing_settings,
- clk_freq = clk_freq)
- self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
+ self.dramcore = gramCore(
+ phy=self.ddrphy,
+ geom_settings=ddrmodule.geom_settings,
+ timing_settings=ddrmodule.timing_settings,
+ clk_freq=clk_freq)
+ self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
- self.drambone = gramWishbone(self.dramcore)
- self._decoder.add(self.drambone.bus, addr=ddr_addr)
+ self.drambone = gramWishbone(self.dramcore)
+ self._decoder.add(self.drambone.bus, addr=ddr_addr)
- self.memory_map = self._decoder.bus.memory_map
+ self.memory_map = self._decoder.bus.memory_map
- self.clk_freq = clk_freq
+ self.clk_freq = clk_freq
- def elaborate(self, platform):
- m = Module()
+ def elaborate(self, platform):
+ m = Module()
- m.submodules.arbiter = self._arbiter
- m.submodules.cpu = self.cpu
+ m.submodules.arbiter = self._arbiter
+ m.submodules.cpu = self.cpu
- m.submodules.decoder = self._decoder
- m.submodules.rom = self.rom
- m.submodules.ram = self.ram
- m.submodules.uart = self.uart
- m.submodules.timer = self.timer
- m.submodules.intc = self.intc
- m.submodules.ddrphy = self.ddrphy
- m.submodules.dramcore = self.dramcore
- m.submodules.drambone = self.drambone
+ m.submodules.decoder = self._decoder
+ m.submodules.rom = self.rom
+ m.submodules.ram = self.ram
+ m.submodules.uart = self.uart
+ m.submodules.timer = self.timer
+ m.submodules.intc = self.intc
+ m.submodules.ddrphy = self.ddrphy
+ m.submodules.dramcore = self.dramcore
+ m.submodules.drambone = self.drambone
- m.submodules.sysclk = SysClocker()
+ m.submodules.sysclk = SysClocker()
- m.d.comb += [
- self._arbiter.bus.connect(self._decoder.bus),
- self.cpu.ip.eq(self.intc.ip),
- ]
+ m.d.comb += [
+ self._arbiter.bus.connect(self._decoder.bus),
+ self.cpu.ip.eq(self.intc.ip),
+ ]
- return m
+ return m
if __name__ == "__main__":
- platform = ECPIX5Platform()
-
- uart_divisor = int(platform.default_clk_frequency // 115200)
- uart_pins = platform.request("uart", 0)
-
- soc = DDR3SoC(
- reset_addr=0x00000000, clk_freq=int(platform.default_clk_frequency),
- rom_addr=0x00000000, rom_size=0x4000,
- rom2_addr=0x7000, rom2_size=0x1000,
- ram_addr=0x00004000, ram_size=0x1000,
- uart_addr=0x00005000, uart_divisor=uart_divisor, uart_pins=uart_pins,
- timer_addr=0x00006000, timer_width=32,
- ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
- ddr_addr=0x10000000
- )
-
- soc.build(do_build=True, do_init=True)
- platform.build(soc, do_program=True)
+ platform = ECPIX5Platform()
+
+ uart_divisor = int(platform.default_clk_frequency // 115200)
+ uart_pins = platform.request("uart", 0)
+
+ soc = DDR3SoC(
+ reset_addr=0x00000000, clk_freq=int(platform.default_clk_frequency),
+ rom_addr=0x00000000, rom_size=0x4000,
+ rom2_addr=0x7000, rom2_size=0x1000,
+ ram_addr=0x00004000, ram_size=0x1000,
+ uart_addr=0x00005000, uart_divisor=uart_divisor, uart_pins=uart_pins,
+ timer_addr=0x00006000, timer_width=32,
+ ddrphy_addr=0x00008000, dramcore_addr=0x00009000,
+ ddr_addr=0x10000000
+ )
+
+ soc.build(do_build=True, do_init=True)
+ platform.build(soc, do_program=True)
projects / gram.git / commitdiff