#define WRITE_VL(vlnext) (h->get_ct_state()->vl = (vlnext))
#define WRITE_UTIDX(value) (h->get_ct_state()->count = (value))
#define WRITE_VF_PC(pcnext) (h->get_ct_state()->vf_pc = (pcnext))
+ #define WRITE_PREC(precision) (h->get_ct_state()->prec = (precision))
#define INSN_RS1 (insn.rs1())
#define INSN_RS2 (insn.rs2())
#define INSN_RS3 (insn.rs3())
#define INSN_RD (insn.rd())
-#define INSN_SEG ((insn.i_imm() >> 9)+1)
+#define INSN_SEG (((reg_t)insn.i_imm() >> 9)+1)
static inline reg_t read_xpr(hwacha_t* h, insn_t insn, uint32_t idx, size_t src)
{
-get_insn_list = $(shell sed 's/DECLARE_INSN(\(.*\),.*,.*)/\1/' $(1))
-get_opcode = $(shell grep \\\<$(2)\\\> $(1) | sed 's/DECLARE_INSN(.*,\(.*\),.*)/\1/')
-
hwacha_subproject_deps = \
riscv \
softfloat \
hwacha_xcpt.h \
decode_hwacha.h \
decode_hwacha_ut.h \
+ decode_hwacha_ut_half.h \
opcodes_hwacha.h \
opcodes_hwacha_ut.h \
+ opcodes_hwacha_ut_half.h \
hwacha_srcs = \
hwacha.cc \
hwacha_disasm.cc \
+ cvt16.cc \
$(hwacha_gen_srcs) \
$(hwacha_ut_gen_srcs) \
+ $(hwacha_ut_half_gen_srcs) \
hwacha_test_srcs =
$(hwacha_ut_gen_srcs): %.cc: insns_ut/%.h insn_template_hwacha_ut.cc
sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut.h,$(subst .cc,,$@))/' > $@
+ hwacha_ut_half_gen_srcs = \
+ $(addsuffix .cc, $(call get_insn_list,$(src_dir)/hwacha/opcodes_hwacha_ut_half.h))
+
+ $(hwacha_ut_half_gen_srcs): %.cc: insns_ut_half/%.h insn_template_hwacha_ut_half.cc
+ sed 's/NAME/$(subst .cc,,$@)/' $(src_dir)/hwacha/insn_template_hwacha_ut_half.cc | sed 's/OPCODE/$(call get_opcode,$(src_dir)/hwacha/opcodes_hwacha_ut_half.h,$(subst .cc,,$@))/' > $@