Added $anyseq cell type

diff --git a/backends/smt2/smt2.cc b/backends/smt2/smt2.cc
index 487f5befbb0b2c8eb9e1210c6c967cdc75b46fab..6bcd1f452dfa75987decc2ed46cdd4cba4176506 100644 (file)
--- a/backends/smt2/smt2.cc
+++ b/backends/smt2/smt2.cc
@@ -417,7 +417,7 @@ struct Smt2Worker
                                return;
                        }
 
-                       if (cell->type == "$anyconst")
+                       if (cell->type.in("$anyconst", "$anyseq"))
                        {
                                registers.insert(cell);
                                decls.push_back(stringf("; yosys-smt2-%s %s#%d %s\n", cell->type.c_str() + 1, get_id(module), idcounter,

diff --git a/examples/smtbmc/demo7.v b/examples/smtbmc/demo7.v
index 75b3865c5bf1b855ee70d7872813fcbf07a17f2e..63f6272f16f46e82bb2c7309c805a4336983b343 100644 (file)
--- a/examples/smtbmc/demo7.v
+++ b/examples/smtbmc/demo7.v
@@ -1,6 +1,7 @@
 // Demo for memory initialization
 
-module demo7 (input [2:0] addr);
+module demo7;
+       wire [2:0] addr = $anyseq;
        reg [15:0] memory [0:7];
 
        initial begin

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 229a3b596824512c7a818d09b1cc4c5cf4ac4686..7c661e8f372aae0bfd31d2e5a02a2d5c730df3cd 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -762,7 +762,7 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
                break;
 
        case AST_FCALL:
-               if (str == "\\$anyconst") {
+               if (str == "\\$anyconst" || str == "\\$anyseq") {
                        if (GetSize(children) == 1) {
                                while (children[0]->simplify(true, false, false, 1, -1, false, true) == true) { }
                                if (children[0]->type != AST_CONSTANT)
@@ -1465,7 +1465,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
                } break;
 
        case AST_FCALL: {
-                       if (str == "\\$anyconst")
+                       if (str == "\\$anyconst" || str == "\\$anyseq")
                        {
                                string myid = stringf("%s$%d", str.c_str() + 1, autoidx++);
                                int width = width_hint;

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 57aa648ce6c76b7a30a24621cb867d3ec8cca8d7..d58b1c283667a7d707dcdd86a7c846c80c7090b4 100644 (file)
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1807,8 +1807,8 @@ skip_dynamic_range_lvalue_expansion:;
                                goto apply_newNode;
                        }
 
-                       // $anyconst is mapped in AstNode::genRTLIL()
-                       if (str == "\\$anyconst") {
+                       // $anyconst and $anyseq are mapped in AstNode::genRTLIL()
+                       if (str == "\\$anyconst" || str == "\\$anyseq") {
                                recursion_counter--;
                                return false;
                        }

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index c730ce5b200cb2b55c6fdbc4bebcd6ca66429653..5bbda5355f8bba87d312db4495614588840f2343 100644 (file)
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -1229,7 +1229,7 @@ rvalue:
                $$ = new AstNode(AST_IDENTIFIER, $2);
                $$->str = *$1;
                delete $1;
-               if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst"))
+               if ($2 == nullptr && formal_mode && ($$->str == "\\$initstate" || $$->str == "\\$anyconst" || $$->str == "\\$anyseq"))
                        $$->type = AST_FCALL;
        } |
        hierarchical_id non_opt_multirange {

diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 8e3f86f698ff65c46e4a79433b35ba9e17848f79..f0ead1e89d0d71cacb012e19718fb2fa866b78ee 100644 (file)
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -118,6 +118,7 @@ struct CellTypes
                setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
                setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true);
+               setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true);
                setup_type("$equiv", {A, B}, {Y}, true);
        }
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b0cda67b4f2d4ec1c0b953d3cdc965ca084606b1..66bbf0427bb01e4c3db41541d53d767e5147f3e6 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1037,7 +1037,7 @@ namespace {
                                return;
                        }
 
-                       if (cell->type == "$anyconst") {
+                       if (cell->type.in("$anyconst", "$anyseq")) {
                                port("\\Y", param("\\WIDTH"));
                                check_expected();
                                return;
@@ -2009,6 +2009,15 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width)
        return sig;
 }
 
+RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width)
+{
+       RTLIL::SigSpec sig = addWire(NEW_ID, width);
+       Cell *cell = addCell(name, "$anyseq");
+       cell->setParam("\\WIDTH", width);
+       cell->setPort("\\Y", sig);
+       return sig;
+}
+
 RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name)
 {
        RTLIL::SigSpec sig = addWire(NEW_ID);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 109e333516ae02b4240fd0375553b36aa8ad6d15..9430dcb3668db1b76d3ea6a16abd3f53efcfc582 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1108,6 +1108,7 @@ public:
        RTLIL::SigBit Oai4Gate (RTLIL::IdString name, RTLIL::SigBit sig_a, RTLIL::SigBit sig_b, RTLIL::SigBit sig_c, RTLIL::SigBit sig_d);
 
        RTLIL::SigSpec Anyconst  (RTLIL::IdString name, int width = 1);
+       RTLIL::SigSpec Anyseq    (RTLIL::IdString name, int width = 1);
        RTLIL::SigSpec Initstate (RTLIL::IdString name);
 };
 

diff --git a/kernel/satgen.h b/kernel/satgen.h
index 792bb3ed71f69a88a8d89cf8cbb3935fddf0d8cc..690f8e337471d129b3d02836029ab218d09602a6 100644 (file)
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -1332,8 +1332,8 @@ struct SatGen
 
                        if (model_undef)
                        {
-                               std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\D"), timestep-1);
-                               std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Q"), timestep);
+                               std::vector<int> undef_d = importUndefSigSpec(cell->getPort("\\Y"), timestep-1);
+                               std::vector<int> undef_q = importUndefSigSpec(cell->getPort("\\Y"), timestep);
 
                                ez->assume(ez->vec_eq(undef_d, undef_q));
                                undefGating(q, qq, undef_q);
@@ -1341,6 +1341,11 @@ struct SatGen
                        return true;
                }
 
+               if (cell->type == "$anyseq")
+               {
+                       return true;
+               }
+
                if (cell->type == "$_BUF_" || cell->type == "$equiv")
                {
                        std::vector<int> a = importDefSigSpec(cell->getPort("\\A"), timestep);

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 7778fe8fd8e78c12c3c0f7076637a639d42ee7f4..a831fdf33b00e04aed8fc20ae92ea287e8f1fb60 100644 (file)
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, and {\tt \$anyconst} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells.
 \end{fixme}
 
 \begin{fixme}

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index b10c858f24b296dda0ba302af5fd323268dc08bc..2c4db1ac6d2f24a5e2671b220cbcee7d621d07eb 100644 (file)
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1334,6 +1334,18 @@ endmodule
 
 // --------------------------------------------------------
 
+module \$anyseq (Y);
+
+parameter WIDTH = 0;
+
+output [WIDTH-1:0] Y;
+
+assign Y = 'bx;
+
+endmodule
+
+// --------------------------------------------------------
+
 module \$equiv (A, B, Y);
 
 input A, B;