mem: Schedule time for DRAM event taking tRAS into account

This patch changes the time the controller is woken up to take the
next scheduling decisions. tRAS is now handled in estimateLatency and
doDRAMAccess and we do not need to worry about it at scheduling
time. The earliest we need to wake up is to do a pre-charge, row
access and column access before the bus becomes free for use.

diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc
index c537006a1c2d9530af3df457f74074f2086558a2..280ab640df0dcbc06192eb074179d4dc23e6af36 100644 (file)
--- a/src/mem/simple_dram.cc
+++ b/src/mem/simple_dram.cc
@@ -1135,12 +1135,11 @@ SimpleDRAM::doDRAMAccess(DRAMPacket* dram_pkt)
 
     // The absolute soonest you have to start thinking about the
     // next request is the longest access time that can occur before
-    // busBusyUntil. Assuming you need to meet tRAS, then precharge,
-    // open a new row, and access, it is ~4*tRCD.
+    // busBusyUntil. Assuming you need to precharge,
+    // open a new row, and access, it is tRP + tRCD + tCL
 
-
-    Tick newTime = (busBusyUntil > 4 * tRCD) ?
-                   std::max(busBusyUntil - 4 * tRCD, curTick()) :
+    Tick newTime = (busBusyUntil > tRP + tRCD + tCL ) ?
+                   std::max(busBusyUntil - (tRP + tRCD + tCL) , curTick()) :
                    curTick();
 
     if (!nextReqEvent.scheduled() && !stopReads){