]
with m.Elif(f_icache_select):
m.d.comb += [
- self.f_busy_o.eq(icache.s2_re & icache.s2_miss),
+ self.f_busy_o.eq(icache.s2_miss),
self.f_instr_o.eq(icache.s2_rdata)
]
with m.Else():
m.d.comb += dba.bus.connect(self.dbus)
wrbuf_port = dbus_arbiter.port(priority=0)
- with m.If(wrbuf_port.cyc):
+ m.d.comb += [
+ wrbuf_port.cyc.eq(wrbuf.r_rdy),
+ wrbuf_port.we.eq(Const(1)),
+ ]
+ with m.If(wrbuf_port.stb):
with m.If(wrbuf_port.ack | wrbuf_port.err):
- m.d.sync += [
- wrbuf_port.cyc.eq(0),
- wrbuf_port.stb.eq(0)
- ]
+ m.d.sync += wrbuf_port.stb.eq(0)
m.d.comb += wrbuf.r_en.eq(1)
with m.Elif(wrbuf.r_rdy):
m.d.sync += [
- wrbuf_port.cyc.eq(1),
wrbuf_port.stb.eq(1),
wrbuf_port.adr.eq(wrbuf_r_data.addr),
wrbuf_port.sel.eq(wrbuf_r_data.mask),
wrbuf_port.dat_w.eq(wrbuf_r_data.data)
]
- m.d.comb += wrbuf_port.we.eq(Const(1))
dcache_port = dba.port(priority=1)
cti = Mux(dcache.bus_last, Cycle.END, Cycle.INCREMENT)
self.m_busy_o.eq(0),
self.m_ld_data_o.eq(0)
]
- with m.Elif(m_dcache_select):
+ with m.Elif(self.m_load & m_dcache_select):
m.d.comb += [
- self.m_busy_o.eq(dcache.s2_re & dcache.s2_miss),
+ self.m_busy_o.eq(dcache.s2_miss),
self.m_ld_data_o.eq(dcache.s2_rdata)
]
with m.Else():