arch-power: Add fields for XS form instructions

This introduces the extended opcode field for XS form
instructions and the sh field which is concatenated
with the SH field for specifying a shift amount for
doubleword operands.

Change-Id: I8f7cb3a2fda33b5b0076ffe12ffebeb5ec1c33a6
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>

diff --git a/src/arch/power/isa/bitfields.isa b/src/arch/power/isa/bitfields.isa
index 8783081e2637a74d24255cf4bf3c57d2b4a11ca4..dfe4683dcf39964d7cd72fbb84e68e2af5fe402a 100644 (file)
--- a/src/arch/power/isa/bitfields.isa
+++ b/src/arch/power/isa/bitfields.isa
@@ -44,6 +44,7 @@ def bitfield XFL_XO        <10:1>;
 def bitfield XFX_XO        <10:1>;
 def bitfield XL_XO         <10:1>;
 def bitfield XO_XO         <9:1>;
+def bitfield XS_XO         <10:2>;
 
 // Register fields
 def bitfield RA            <20:16>;

diff --git a/src/arch/power/types.hh b/src/arch/power/types.hh
index 4ce18649499bb9e6cbdefa599a9e1be4caa6b7da..8ba09f23ba4bad0163e78e201b09ad6bba9311b6 100644 (file)
--- a/src/arch/power/types.hh
+++ b/src/arch/power/types.hh
@@ -46,6 +46,7 @@ BitUnion32(ExtMachInst)
 
     // Shifts and masks
     Bitfield<15, 11> sh;
+    Bitfield<1>      shn;
     Bitfield<10,  6> mb;
     Bitfield< 5,  1> me;