remove unneeded imports in sim test cases

diff --git a/src/openpower/simulator/test_div_sim.py b/src/openpower/simulator/test_div_sim.py
index 394c1a968963c0dada7c94aae754f4ad55c8b5c1..0cad521b740b15e142438b4a1900cfd3a47c4f0e 100644 (file)
--- a/src/openpower/simulator/test_div_sim.py
+++ b/src/openpower/simulator/test_div_sim.py
@@ -1,19 +1,11 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
 import unittest
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form, SPR,
-                                     get_signal_name, get_csv)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
+from nmutil.formaltest import FHDLTestCase
 from openpower.simulator.program import Program
 from openpower.simulator.qemu import run_program
 from openpower.decoder.isa.all import ISA
 from openpower.test.common import TestCase
 from openpower.simulator.test_sim import DecoderBase
+from openpower.endian import bigendian
 
 
 
@@ -29,7 +21,7 @@ class DivTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "divw  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_1_divw_(self):
@@ -37,7 +29,7 @@ class DivTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "divw.  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_2_divw_(self):
@@ -45,7 +37,7 @@ class DivTestCases(FHDLTestCase):
                "addi 2, 0, 0x5678",
                "divw.  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_1_divwe(self):
@@ -53,7 +45,7 @@ class DivTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "divwe  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_2_divweu(self):
@@ -61,7 +53,7 @@ class DivTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "divweu  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_4_moduw(self):
@@ -69,7 +61,7 @@ class DivTestCases(FHDLTestCase):
                "addi 2, 0, 0x1234",
                "moduw  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_5_div_regression(self):
@@ -79,7 +71,7 @@ class DivTestCases(FHDLTestCase):
                "neg 1, 1",
                "divwo  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,
@@ -102,7 +94,7 @@ class DivZeroTestCases(FHDLTestCase):
                "addi 2, 0, 0x0",
                "divw  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_1_divwe(self):
@@ -110,7 +102,7 @@ class DivZeroTestCases(FHDLTestCase):
                "addi 2, 0, 0x0",
                "divwe  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_2_divweu(self):
@@ -118,7 +110,7 @@ class DivZeroTestCases(FHDLTestCase):
                "addi 2, 0, 0x0",
                "divweu  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def test_4_moduw(self):
@@ -126,7 +118,7 @@ class DivZeroTestCases(FHDLTestCase):
                "addi 2, 0, 0x0",
                "moduw  3, 1, 2",
                ]
-        with Program(lst) as program:
+        with Program(lst, bigendian) as program:
             self.run_tst_program(program, [1, 2, 3])
 
     def run_tst_program(self, prog, initial_regs=None, initial_sprs=None,

diff --git a/src/openpower/simulator/test_helloworld_sim.py b/src/openpower/simulator/test_helloworld_sim.py
index 85cfe4aa3c02be4e80a40d453e9cce06cd12d1ba..03d1e4a4273c1422c1c772ccfc06809fa660ede0 100644 (file)
--- a/src/openpower/simulator/test_helloworld_sim.py
+++ b/src/openpower/simulator/test_helloworld_sim.py
@@ -1,17 +1,7 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
 import unittest
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form, SPR,
-                                     get_signal_name, get_csv)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
+from nmutil.formaltest import FHDLTestCase
 from openpower.simulator.program import Program
 from openpower.simulator.qemu import run_program
-from openpower.decoder.isa.all import ISA
 from openpower.test.common import TestCase
 from openpower.simulator.test_sim import DecoderBase
 from openpower.endian import bigendian

diff --git a/src/openpower/simulator/test_mul_sim.py b/src/openpower/simulator/test_mul_sim.py
index 52dc23f288060f1de9217635185730f5a7f24400..df1692ffbfc480ca976e663ce765d6b02a22f4f7 100644 (file)
--- a/src/openpower/simulator/test_mul_sim.py
+++ b/src/openpower/simulator/test_mul_sim.py
@@ -1,17 +1,7 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
 import unittest
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form, SPRfull,
-                                     get_signal_name, get_csv)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
+from nmutil.formaltest import FHDLTestCase
 from openpower.simulator.program import Program
 from openpower.simulator.qemu import run_program
-from openpower.decoder.isa.all import ISA
 from openpower.test.common import TestCase
 from openpower.simulator.test_sim import DecoderBase
 from openpower.endian import bigendian

diff --git a/src/openpower/simulator/test_shift_sim.py b/src/openpower/simulator/test_shift_sim.py
index bed9bf45f24cc3894479263c1bbd50744df10cf1..47e93665671fc6966b8cd1fcac47f20c472ce2e0 100644 (file)
--- a/src/openpower/simulator/test_shift_sim.py
+++ b/src/openpower/simulator/test_shift_sim.py
@@ -1,14 +1,5 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
-from nmutil.formaltest import FHDLTestCase
 import unittest
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form, SPR,
-                                     get_signal_name, get_csv)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
+from nmutil.formaltest import FHDLTestCase
 from openpower.simulator.program import Program
 from openpower.simulator.qemu import run_program
 from openpower.decoder.isa.all import ISA

diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py
index a18b8bce1d595222c8d99d306f4110852058491c..8c02081925d47669480c9fbeee37f48af3932478 100644 (file)
--- a/src/openpower/simulator/test_sim.py
+++ b/src/openpower/simulator/test_sim.py
@@ -1,13 +1,8 @@
-from nmigen import Module, Signal
+import unittest
+from nmigen import Module
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
-import unittest
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form,
-                                     get_signal_name, get_csv)
+from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)
 from openpower.simulator.program import Program
 from openpower.simulator.qemu import run_program

diff --git a/src/openpower/simulator/test_trap_sim.py b/src/openpower/simulator/test_trap_sim.py
index b6c95803128e82f95282bb412328f8e53d1206a2..e8f08b3b44cbd3a19ea54220572e325b10119697 100644 (file)
--- a/src/openpower/simulator/test_trap_sim.py
+++ b/src/openpower/simulator/test_trap_sim.py
@@ -1,17 +1,7 @@
-from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
-from openpower.decoder.power_decoder import (create_pdecode)
-from openpower.decoder.power_enums import (Function, MicrOp,
-                                     In1Sel, In2Sel, In3Sel,
-                                     OutSel, RC, LdstLen, CryIn,
-                                     single_bit_flags, Form, SPR,
-                                     get_signal_name, get_csv)
-from openpower.decoder.power_decoder2 import (PowerDecode2)
 from openpower.simulator.program import Program
 from openpower.simulator.qemu import run_program
-from openpower.decoder.isa.all import ISA
 from openpower.test.common import TestCase
 from openpower.simulator.test_sim import DecoderBase
 from openpower.endian import bigendian #XXX HACK!