[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
authorbugzilla-daemon <bugzilla-daemon@libre-riscv.org>
Sat, 14 Mar 2020 10:30:26 +0000 (10:30 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sat, 14 Mar 2020 10:30:27 +0000 (10:30 +0000)
f8/5fd0a981d0a9f187dd4452a6989943f77b4c28 [new file with mode: 0644]

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+Date: Sat, 14 Mar 2020 10:30:26 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-241-13-A4tHSfmnCF@http.bugs.libre-riscv.org/>
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+Subject: [libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of
+ standards
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