Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only power cores and spec...
authorBenjamin Herrenschmidt <benh@ozlabs.org>
Wed, 13 May 2020 01:41:00 +0000 (11:41 +1000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Wed, 13 May 2020 09:15:57 +0000 (10:15 +0100)
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+Message-ID: <ba6dfcfcac4cb37dab95ba1669f68f57f01347d1.camel@ozlabs.org>
+From: Benjamin Herrenschmidt <benh@ozlabs.org>
+To: Hugh Blemings <hugh@blemings.org>, Jacob Lifshay
+ <programmerjake@gmail.com>, 
+ openpower-hdl-cores@mailinglist.openpowerfoundation.org
+Date: Wed, 13 May 2020 11:41:00 +1000
+In-Reply-To: <ec667579-06e2-ff44-4604-b160149feaa3@blemings.org>
+References: <CAC2bXD6LVtrMh7RT=11ZVypujcJRaMokG7XuBwF87veBiMMDLQ@mail.gmail.com>
+ <ec667579-06e2-ff44-4604-b160149feaa3@blemings.org>
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+X-Mailman-Approved-At: Wed, 13 May 2020 10:15:55 +0100
+Subject: Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] little-endian only
+ power cores and spec compliance
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