);\r
endmodule\r
\r
-(* blackbox *)\r
+(* blackbox *) (* keep *)\r
module CC_SERDES #(\r
parameter SERDES_CFG = ""\r
)(\r
input VALID\r
);\r
endmodule\r
+\r
+(* blackbox *)\r
+module CC_FIFO_40K (\r
+ output A_ECC_1B_ERR,\r
+ output B_ECC_1B_ERR,\r
+ output A_ECC_2B_ERR,\r
+ output B_ECC_2B_ERR,\r
+ // FIFO pop port\r
+ output [39:0] A_DO,\r
+ output [39:0] B_DO,\r
+ (* clkbuf_sink *)\r
+ input A_CLK,\r
+ input A_EN,\r
+ // FIFO push port\r
+ input [39:0] A_DI,\r
+ input [39:0] B_DI,\r
+ input [39:0] A_BM,\r
+ input [39:0] B_BM,\r
+ (* clkbuf_sink *)\r
+ input B_CLK,\r
+ input B_EN,\r
+ input B_WE,\r
+ // FIFO control\r
+ input F_RST_N,\r
+ input [12:0] F_ALMOST_FULL_OFFSET,\r
+ input [12:0] F_ALMOST_EMPTY_OFFSET,\r
+ // FIFO status signals\r
+ output F_FULL,\r
+ output F_EMPTY,\r
+ output F_ALMOST_FULL,\r
+ output F_ALMOST_EMPTY,\r
+ output F_RD_ERROR,\r
+ output F_WR_ERROR,\r
+ output [15:0] F_RD_PTR,\r
+ output [15:0] F_WR_PTR\r
+);\r
+ // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r
+ parameter LOC = "UNPLACED";\r
+\r
+ // Offset configuration\r
+ parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;\r
+ parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;\r
+\r
+ // Port Widths\r
+ parameter A_WIDTH = 0;\r
+ parameter B_WIDTH = 0;\r
+\r
+ // RAM and Write Modes\r
+ parameter RAM_MODE = "SDP"; // "TPD" or "SDP"\r
+ parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"\r
+\r
+ // Inverting Control Pins\r
+ parameter A_CLK_INV = 1'b0;\r
+ parameter B_CLK_INV = 1'b0;\r
+ parameter A_EN_INV = 1'b0;\r
+ parameter B_EN_INV = 1'b0;\r
+ parameter A_WE_INV = 1'b0;\r
+ parameter B_WE_INV = 1'b0;\r
+\r
+ // Output Register\r
+ parameter A_DO_REG = 1'b0;\r
+ parameter B_DO_REG = 1'b0;\r
+\r
+ // Error Checking and Correction\r
+ parameter A_ECC_EN = 1'b0;\r
+ parameter B_ECC_EN = 1'b0;\r
+endmodule\r
assign en = (EN_INV) ? ~EN : EN;\r
assign sr = (SR_INV) ? ~SR : SR;\r
\r
- initial Q = 0;\r
+ initial Q = 1'bX;\r
\r
always @(posedge clk or posedge sr)\r
begin\r
assign en = (G_INV) ? ~G : G;\r
assign sr = (SR_INV) ? ~SR : SR;\r
\r
- initial Q = 0;\r
+ initial Q = 1'bX;\r
\r
always @(*)\r
begin\r
module CC_MX2 (\r
input D0, D1,\r
input S0,\r
- output reg Y\r
+ output Y\r
);\r
- always @(*) begin\r
- case (S0)\r
- 1'b0: Y <= D0;\r
- 1'b1: Y <= D1;\r
- endcase\r
- end\r
+ assign Y = S0 ? D1 : D0;\r
\r
specify\r
(D0 => Y) = (0:0:0, 0:0:0);\r
module CC_MX4 (\r
input D0, D1, D2, D3,\r
input S0, S1,\r
- output reg Y\r
+ output Y\r
);\r
- always @(*) begin\r
- case ({S1, S0})\r
- 2'b00: Y <= D0;\r
- 2'b01: Y <= D1;\r
- 2'b10: Y <= D2;\r
- 2'b11: Y <= D3;\r
- endcase\r
- end\r
+ assign Y = S1 ? (S0 ? D3 : D2) :\r
+ (S0 ? D1 : D0);\r
\r
specify\r
(D0 => Y) = (0:0:0, 0:0:0);\r
input D0, D1, D2, D3,\r
input D4, D5, D6, D7,\r
input S0, S1, S2,\r
- output reg Y\r
+ output Y\r
);\r
- always @(*) begin\r
- case ({S2, S1, S0})\r
- 3'b000: Y <= D0;\r
- 3'b001: Y <= D1;\r
- 3'b010: Y <= D2;\r
- 3'b011: Y <= D3;\r
- 3'b100: Y <= D4;\r
- 3'b101: Y <= D5;\r
- 3'b110: Y <= D6;\r
- 3'b111: Y <= D7;\r
- endcase\r
- end\r
+ assign Y = S2 ? (S1 ? (S0 ? D7 : D6) :\r
+ (S0 ? D5 : D4)) :\r
+ (S1 ? (S0 ? D3 : D2) :\r
+ (S0 ? D1 : D0));\r
\r
specify\r
(D0 => Y) = (0:0:0, 0:0:0);\r
endmodule\r
\r
\r
-(* blackbox *)\r
module CC_BRAM_20K (\r
output [19:0] A_DO,\r
output [19:0] B_DO,\r
endmodule\r
\r
\r
-(* blackbox *)\r
module CC_BRAM_40K (\r
output [39:0] A_DO,\r
output [39:0] B_DO,\r
end\r
endgenerate\r
endmodule\r
-\r
-\r
-(* blackbox *)\r
-module CC_FIFO_40K (\r
- output A_ECC_1B_ERR,\r
- output B_ECC_1B_ERR,\r
- output A_ECC_2B_ERR,\r
- output B_ECC_2B_ERR,\r
- // FIFO pop port\r
- output [39:0] A_DO,\r
- output [39:0] B_DO,\r
- (* clkbuf_sink *)\r
- input A_CLK,\r
- input A_EN,\r
- // FIFO push port\r
- input [39:0] A_DI,\r
- input [39:0] B_DI,\r
- input [39:0] A_BM,\r
- input [39:0] B_BM,\r
- (* clkbuf_sink *)\r
- input B_CLK,\r
- input B_EN,\r
- input B_WE,\r
- // FIFO control\r
- input F_RST_N,\r
- input [12:0] F_ALMOST_FULL_OFFSET,\r
- input [12:0] F_ALMOST_EMPTY_OFFSET,\r
- // FIFO status signals\r
- output F_FULL,\r
- output F_EMPTY,\r
- output F_ALMOST_FULL,\r
- output F_ALMOST_EMPTY,\r
- output F_RD_ERROR,\r
- output F_WR_ERROR,\r
- output [15:0] F_RD_PTR,\r
- output [15:0] F_WR_PTR\r
-);\r
- // Location format: D(0..N-1)X(0..3)Y(0..7) or UNPLACED\r
- parameter LOC = "UNPLACED";\r
-\r
- // Offset configuration\r
- parameter [12:0] ALMOST_FULL_OFFSET = 12'b0;\r
- parameter [12:0] ALMOST_EMPTY_OFFSET = 12'b0;\r
-\r
- // Port Widths\r
- parameter A_WIDTH = 0;\r
- parameter B_WIDTH = 0;\r
-\r
- // RAM and Write Modes\r
- parameter RAM_MODE = "SDP"; // "TPD" or "SDP"\r
- parameter FIFO_MODE = "SYNC"; // "ASYNC" or "SYNC"\r
-\r
- // Inverting Control Pins\r
- parameter A_CLK_INV = 1'b0;\r
- parameter B_CLK_INV = 1'b0;\r
- parameter A_EN_INV = 1'b0;\r
- parameter B_EN_INV = 1'b0;\r
- parameter A_WE_INV = 1'b0;\r
- parameter B_WE_INV = 1'b0;\r
-\r
- // Output Register\r
- parameter A_DO_REG = 1'b0;\r
- parameter B_DO_REG = 1'b0;\r
-\r
- // Error Checking and Correction\r
- parameter A_ECC_EN = 1'b0;\r
- parameter B_ECC_EN = 1'b0;\r
-endmodule\r
*\r
*/\r
\r
-module \$__inpad (input I, output Y);\r
- CC_IBUF /*#(\r
- .PIN_NAME("UNPLACED"),\r
- .V_IO("UNDEFINED"),\r
- .PULLUP(1'bx),\r
- .PULLDOWN(1'bx),\r
- .KEEPER(1'bx),\r
- .SCHMITT_TRIGGER(1'bx),\r
- .DELAY_IBF(4'bx),\r
- .FF_IBF(1'bx)\r
- )*/ _TECHMAP_REPLACE_ (\r
- .I(I),\r
- .Y(Y)\r
- );\r
-endmodule\r
-\r
-module \$__outpad (input A, output O);\r
- CC_OBUF /*#(\r
- .PIN_NAME("UNPLACED"),\r
- .V_IO("UNDEFINED"),\r
- .SLEW("UNDEFINED"),\r
- .DRIVE(1'bx),\r
- .DELAY_OBF(4'bx),\r
- .FF_OBF(1'bx)\r
- )*/ _TECHMAP_REPLACE_ (\r
- .A(A),\r
- .O(O)\r
- );\r
-endmodule\r
-\r
module \$__toutpad (input A, input OE, output O);\r
CC_TOBUF /*#(\r
.PIN_NAME("UNPLACED"),\r
*
*/
-`define MAX(a,b) (a > b ? a : b)
-`define MIN(a,b) (a < b ? a : b)
+`define MAX(a,b) ((a) > (b) ? (a) : (b))
+`define MIN(a,b) ((a) < (b) ? (a) : (b))
(* techmap_celltype = "$mul $__mul" *)
module \$__MULMXN (A, B, Y);
run("opt -undriven -fine");\r
}\r
\r
- if (check_label("map_addf", "(skip if '-noaddf')"))\r
+ if (check_label("map_gates"))\r
{\r
std::string techmap_args = "";\r
if (!noaddf) {\r
{\r
if (!noiopad) {\r
run("iopadmap -bits "\r
- "-inpad $__inpad Y:I "\r
- "-outpad $__outpad A:O "\r
+ "-inpad CC_IBUF Y:I "\r
+ "-outpad CC_OBUF A:O "\r
"-toutpad $__toutpad OE:A:O "\r
"-tinoutpad $__tinoutpad OE:Y:A:IO"\r
);\r
if (check_label("map_regs"))\r
{\r
run("opt_clean");\r
- run("dfflegalize -cell $_DFF_?_ 0 -cell $_DFF_???_ 0 "\r
- "-cell $_DFFE_??_ 0 -cell $_DFFE_????_ 0 "\r
- "-cell $_DLATCH_?_ x -cell $_DLATCH_???_ x"\r
- );\r
+ run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");\r
run("techmap -map +/gatemate/reg_map.v");\r
run("opt_expr -mux_undef");\r
run("simplemap");\r
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