Merge pull request #3282 from nakengelhardt/verific_loop_rams

verific: allow memories to be inferred in loops

diff --git a/Makefile b/Makefile
index 38bafc2f188a99a24efadd5bd1e498acc04ad254..1a73e726f10a897d3ce539364dd233537b571359 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -129,7 +129,7 @@ LDFLAGS += -rdynamic
 LDLIBS += -lrt
 endif
 
-YOSYS_VER := 0.16+31
+YOSYS_VER := 0.16+34
 GIT_REV := $(shell git -C $(YOSYS_SRC) rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
 OBJS = kernel/version_$(GIT_REV).o
 

diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc
index ceea725d8cadbe92cc5fdb63f8386c50620b8f3e..1ddc13f903c993b9c9a79b1df3e70e9b45ec08b3 100644 (file)
--- a/passes/memory/memory_share.cc
+++ b/passes/memory/memory_share.cc
@@ -82,6 +82,11 @@ struct MemoryShareWorker
                log("Consolidating read ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
 
                bool changed = false;
+               int abits = 0;
+               for (auto &port: mem.rd_ports) {
+                       if (GetSize(port.addr) > abits)
+                               abits = GetSize(port.addr);
+               }
                for (int i = 0; i < GetSize(mem.rd_ports); i++)
                {
                        auto &port1 = mem.rd_ports[i];
@@ -114,6 +119,8 @@ struct MemoryShareWorker
                                int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
                                SigSpec addr1 = sigmap_xmux(port1.addr);
                                SigSpec addr2 = sigmap_xmux(port2.addr);
+                               addr1.extend_u0(abits);
+                               addr2.extend_u0(abits);
                                if (GetSize(addr1) <= wide_log2)
                                        continue;
                                if (GetSize(addr2) <= wide_log2)
@@ -192,6 +199,11 @@ struct MemoryShareWorker
                log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(mem.memid));
 
                bool changed = false;
+               int abits = 0;
+               for (auto &port: mem.wr_ports) {
+                       if (GetSize(port.addr) > abits)
+                               abits = GetSize(port.addr);
+               }
                for (int i = 0; i < GetSize(mem.wr_ports); i++)
                {
                        auto &port1 = mem.wr_ports[i];
@@ -216,6 +228,8 @@ struct MemoryShareWorker
                                int wide_log2 = std::max(port1.wide_log2, port2.wide_log2);
                                SigSpec addr1 = sigmap_xmux(port1.addr);
                                SigSpec addr2 = sigmap_xmux(port2.addr);
+                               addr1.extend_u0(abits);
+                               addr2.extend_u0(abits);
                                if (GetSize(addr1) <= wide_log2)
                                        continue;
                                if (GetSize(addr2) <= wide_log2)

diff --git a/passes/opt/opt_dff.cc b/passes/opt/opt_dff.cc
index 73d674c8d420c21803679ce5605a02e76a77bd5d..0ad4acec2167447f2c5843d29c529a1f2e4ef586 100644 (file)
--- a/passes/opt/opt_dff.cc
+++ b/passes/opt/opt_dff.cc
@@ -554,7 +554,7 @@ struct OptDffWorker
                                        // The D input path is effectively useless, so remove it (this will be a const-input D latch, SR latch, or a const driver).
                                        log("Handling D = Q on %s (%s) from module %s (removing D path).\n",
                                                        log_id(cell), log_id(cell->type), log_id(module));
-                                       ff.has_clk = ff.has_ce = false;
+                                       ff.has_gclk = ff.has_clk = ff.has_ce = false;
                                        changed = true;
                                }
                        }