Re: [libre-riscv-dev] cache SRAM organisation

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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Date: Thu, 26 Mar 2020 21:08:04 +0100
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+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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+Luke Kenneth Casson Leighton schreef op do 26-03-2020 om 15:15 [+0000]:
+> On Thursday, March 26, 2020, Staf Verhaegen <staf@fibraservi.eu> wrote:
+> > I can understand you do this to implement functional units withconfigur=
+able pipeline length but I would strongly discourage to pipelineregister fi=
+les after each other .
+>=20
+>=20
+> "pipeline register files after each other"? apologies i am not clear what=
+you mean, here.  do you mean "don't do write-thru on the Regfile"?
+
+No I meant for example connecting the output of one port of an asynchronous=
+ RAM to for example the address input of another port of an asynchronous RA=
+M.
+
+greets,
+Staf.
+
+
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