[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Sun, 31 May 2020 16:42:02 +0000 (16:42 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sun, 31 May 2020 16:42:04 +0000 (17:42 +0100)
0f/5f5aab9b051e0218fd6131397ae75b475d57b4 [new file with mode: 0644]

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+Date: Sun, 31 May 2020 16:42:02 +0000
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+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
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+Message-ID: <bug-336-13-5dCVp6RVTR@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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