microwatt_tutorial: Add gtkwave dep, verilator doc links, new section on verilator...

diff --git a/HDL_workflow/microwatt_tutorial.mdwn b/HDL_workflow/microwatt_tutorial.mdwn
index 1f521567dfd0915995df75f77737d379dd7ee5ba..85f9897279bbdc4c94b27f04ce745330b284c4b2 100644 (file)
--- a/HDL_workflow/microwatt_tutorial.mdwn
+++ b/HDL_workflow/microwatt_tutorial.mdwn
@@ -5,6 +5,8 @@ useful links:
 * Original Microwatt Libre-SOC page: [[microwatt]]
 * [Libre-SOC Microwatt repo branch](https://git.libre-soc.org/?p=microwatt.git;a=tree;hb=refs/heads/verilator_trace)
 * [Libre-SOC devscripts repo](https://git.libre-soc.org/?p=dev-env-setup.git;a=tree)
+* [Verilator docs, commands](https://verilator.org/guide/latest/exe_verilator.html)
+* [Verilator runtime command documentation](https://verilator.org/guide/latest/exe_sim.html)
 
 ## Setting up chroot
 
@@ -16,6 +18,7 @@ useful links:
     (microwatt):# ./install-hdl-apt-reqs
     (microwatt):# ./verilator-install
     (microwatt):# ./hdl-tools-yosys
+    (microwatt):# apt install gtkwave -y
     (microwatt):$ cd ~/src/
     (microwatt):$ git clone https://git.libre-soc.org/git/microwatt.git
     (microwatt):$ git checkout verilator_trace
@@ -32,6 +35,8 @@ don't redefine:
 ./ghdl.so':/usr/local/bin/../share/yosys/plugins/**ghdl.so.so**`)
 [IRC](https://libre-soc.org/irclog/%23libre-soc.2023-01-25.log.html#t2023-01-25T11:10:47)
 
+## Running Verilator sim
+
 To run the Verilator simulation, set verilator as the target:
 
     (microwatt):$ export FPGA_TARGET=verilator
@@ -41,16 +46,15 @@ Compile the verilator simulation binary
     (microwatt):$ make microwatt-verilator
 
 The Libre-SOC microwatt tutorial then shows the following command to time how
-long the sim takes to run:
+long the sim takes to run (TODO: Find which args needed exactly):
 
-    (microwatt):$ time ./microwatt-verilator
+    (microwatt):$ time ./microwatt-verilator +verilator+[SOME ARGS]
 
-No additional arguments to the binary are specified.
 
 * [Libre-SOC Microwatt repo branch, Makefile](https://git.libre-soc.org/?p=microwatt.git;a=blob;f=Makefile;h=610f48d8c89be6d5b9902d7f1bf61f8b6d98ffc0;hb=refs/heads/verilator_trace)
 
-In the Makefile, I can see that `RAM_INIT_FILE` (line #144) is specified as
-`helloworld.hex` (the Microwatt 'lightbulb' example code).
+In the Makefile, the `RAM_INIT_FILE` (line #144) is specified as
+`hello_world.hex` (the Microwatt 'lightbulb' example code).
 The Makefile uses this `RAM_INIT_FILE` argument for generating the
 `microwatt.v` verilog file (line #249).
 Finally, to generate the `microwatt-verilator` binary, `microwatt.v` is pulled
@@ -59,3 +63,9 @@ in as a dependency (line #254).
 That's good, means that the verilator sim binary *should already have the
 compiled binary in RAM*.
 
+## Verilator runtime commands
+A few examples:
+
+    # Show the version of verilator being used
+    (microwatt):$ ./microwatt-verilator +verilator+version
+