class Blinky(Elaboratable):
- def __init__(self, clk_name):
- self.clk_name = clk_name
-
def elaborate(self, platform):
m = Module()
- clk = platform.request(self.clk_name)
- clk_freq = platform.get_clock_constraint(clk)
+ clk = platform.request(platform.default_clk)
m.domains.sync = ClockDomain()
m.d.comb += ClockSignal().eq(clk.i)
break
leds = Cat(led.o for led in leds)
+ clk_freq = platform.default_clk_frequency
ctr = Signal(max=int(clk_freq//2), reset=int(clk_freq//2) - 1)
with m.If(ctr == 0):
m.d.sync += ctr.eq(ctr.reset)
return m
-def build_and_program(platform_cls, clk_name, **kwargs):
- platform_cls().build(Blinky(clk_name), do_program=True, **kwargs)
+def build_and_program(platform_cls, **kwargs):
+ platform_cls().build(Blinky(), do_program=True, **kwargs)
class BlackIcePlatform(LatticeICE40Platform):
- device = "iCE40HX4K"
- package = "TQ144"
- resources = [
+ device = "iCE40HX4K"
+ package = "TQ144"
+ default_clk = "clk100"
+ resources = [
Resource("clk100", 0, Pins("129", dir="i"),
Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
),
Attrs(IO_STANDARD="SB_LVCMOS33"),
),
]
-
- connectors = [
+ connectors = [
Connector("pmod", 0, " 94 91 88 85 - - 95 93 90 87 - -"), # PMOD1/2
Connector("pmod", 1, "105 102 99 97 - - 104 101 98 96 - -"), # PMOD3/4
Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"), # PMOD5/6
if __name__ == "__main__":
- from ._blinky import Blinky
- p = BlackIcePlatform()
- p.build(Blinky("clk100"), do_program=True)
+ from ._blinky import build_and_program
+ build_and_program(BlackIcePlatform)
class BlackIceIIPlatform(LatticeICE40Platform):
- device = "iCE40HX4K"
- package = "TQ144"
- resources = [
+ device = "iCE40HX4K"
+ package = "TQ144"
+ default_clk = "clk100"
+ resources = [
Resource("clk100", 0, Pins("129", dir="i"),
Clock(100e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")
),
Attrs(IO_STANDARD="SB_LVCMOS33"),
),
]
-
- connectors = [
+ connectors = [
Connector("pmod", 0, " 94 91 88 85 - - 95 93 90 87 - -"), # PMOD1/2
Connector("pmod", 1, "105 102 99 97 - - 104 101 98 96 - -"), # PMOD3/4
Connector("pmod", 2, "143 114 112 107 - - 144 113 110 106 - -"), # PMOD5/6
if __name__ == "__main__":
- from ._blinky import Blinky
- p = BlackIceIIPlatform()
- p.build(Blinky("clk100"), do_program=True)
+ from ._blinky import build_and_program
+ build_and_program(BlackIceIIPlatform)
class ICE40HX1KBlinkEVNPlatform(LatticeICE40Platform):
- device = "iCE40HX1K"
- package = "VQ100"
- resources = [
+ device = "iCE40HX1K"
+ package = "VQ100"
+ default_clk = "clk3p3"
+ resources = [
Resource("clk3p3", 0, Pins("13", dir="i"), Clock(3.3e6),
Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
- connectors = [
+ connectors = [
Connector("pmod", 1, "10 9 8 7 - - 4 3 2 1 - -"), # J1
Connector("pmod", 5, "40 42 62 64 - - 37 41 63 45 - -"), # J5
Connector("pmod", 6, "25 24 21 20 - - 26 27 28 33 - -"), # J6
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(ICE40HX1KBlinkEVNPlatform, "clk3p3")
+ build_and_program(ICE40HX1KBlinkEVNPlatform)
class ICE40HX8KBEVNPlatform(LatticeICE40Platform):
- device = "iCE40HX8K"
- package = "CT256"
- resources = [
+ device = "iCE40HX8K"
+ package = "CT256"
+ default_clk = "clk12"
+ resources = [
Resource("clk12", 0, Pins("J3", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
- connectors = [
+ connectors = [
Connector("j", 1, # J1
"A16 - A15 B15 B13 B14 - - B12 B11"
"A11 B10 A10 C9 - - A9 B9 B8 A7"
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(ICE40HX8KBEVNPlatform, "clk12")
+ build_and_program(ICE40HX8KBEVNPlatform)
class ICEBreakerPlatform(LatticeICE40Platform):
- device = "iCE40UP5K"
- package = "SG48"
- resources = [
+ device = "iCE40UP5K"
+ package = "SG48"
+ default_clk = "clk12"
+ resources = [
Resource("clk12", 0, Pins("35", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
from ._blinky import Blinky
p = ICEBreakerPlatform()
p.add_resources(p.break_off_pmod)
- p.build(Blinky("clk12"), do_program=True)
+ p.build(Blinky(), do_program=True)
class ICEStickPlatform(LatticeICE40Platform):
- device = "iCE40HX1K"
- package = "TQ144"
- resources = [
+ device = "iCE40HX1K"
+ package = "TQ144"
+ default_clk = "clk12"
+ resources = [
Resource("clk12", 0, Pins("21", dir="i"),
Clock(12e6), Attrs(GLOBAL="1", IO_STANDARD="SB_LVCMOS33")),
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")
),
]
- connectors = [
+ connectors = [
Connector("pmod", 0, "78 79 80 81 - - 87 88 90 91 - -"), # J2
Connector("j", 1, "- - 112 113 114 115 116 117 118 119"), # J1
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(ICEStickPlatform, "clk12")
+ build_and_program(ICEStickPlatform)
class KC705Platform(Xilinx7SeriesPlatform):
- device = "xc7k325t"
- package = "ffg900"
- speed = "2"
- resources = [
+ device = "xc7k325t"
+ package = "ffg900"
+ speed = "2"
+ default_clk = "clk156"
+ resources = [
Resource("clk156", 0, DiffPairs("K28", "K29", dir="i"),
Clock(156e6), Attrs(IOSTANDARD="LVDS_25")),
attrs=Attrs(IOSTANDARD="LVCMOS33")
),
]
- connectors = []
+ connectors = []
def toolchain_program(self, products, name):
openocd = os.environ.get("OPENOCD", "openocd")
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(KC705Platform, "clk156")
+ build_and_program(KC705Platform)
class TinyFPGABXPlatform(LatticeICE40Platform):
- device = "iCE40LP8K"
- package = "CM81"
- resources = [
+ device = "iCE40LP8K"
+ package = "CM81"
+ default_clk = "clk16"
+ resources = [
Resource("clk16", 0, Pins("B2", dir="i"),
Clock(16e6), Attrs(IO_STANDARD="SB_LVCMOS33")),
cs="F7", clk="G7", mosi="G6", miso="H7", wp="H4", hold="J8",
attrs=Attrs(IO_STANDARD="SB_LVCMOS33")),
]
- connectors = [
+ connectors = [
Connector("gpio", 0,
# Left side of the board
# 1 2 3 4 5 6 7 8 9 10 11 12 13
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(TinyFPGABXPlatform, "clk16")
+ build_and_program(TinyFPGABXPlatform)
class VersaECP5Platform(LatticeECP5Platform):
- device = "LFE5UM-45F"
- package = "BG381"
- speed = "8"
- resources = [
+ device = "LFE5UM-45F"
+ package = "BG381"
+ speed = "8"
+ default_clk = "clk100"
+ resources = [
Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
Clock(100e6), Attrs(IO_TYPE="LVDS")),
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(VersaECP5Platform, "clk100")
+ build_and_program(VersaECP5Platform)
class VersaECP55GPlatform(VersaECP5Platform):
- device = "LFE5UM5G-45F"
+ device = "LFE5UM5G-45F"
# Everything else is identical between 3G and 5G Versa boards.
if __name__ == "__main__":
from ._blinky import build_and_program
- build_and_program(VersaECP55GPlatform, "clk100")
+ build_and_program(VersaECP55GPlatform)