[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be...
authorbugzilla-daemon <bugzilla-daemon@libre-soc.org>
Sun, 7 Jun 2020 20:35:32 +0000 (20:35 +0000)
committerlibre-riscv-dev <libre-riscv-dev@lists.libre-riscv.org>
Sun, 7 Jun 2020 20:35:34 +0000 (21:35 +0100)
cf/423ad38d934f59162b942029131731da19c1aa [new file with mode: 0644]

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+Date: Sun, 07 Jun 2020 20:35:32 +0000
+X-Bugzilla-Reason: CC
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Source Code
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: cestrauss@gmail.com
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+Message-ID: <bug-336-13-W6ctgRlhYC@https.bugs.libre-soc.org/>
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+Auto-Submitted: auto-generated
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+Subject: [libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA
+ (src1) can be zero
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