Refactorin of common code

diff --git a/src/soc/consts.py b/src/soc/consts.py
index c06e6bc76d00ee1721ba269644d57865773592f6..fe29743e6858eca62c8651c180abd553ef7539b8 100644 (file)
--- a/src/soc/consts.py
+++ b/src/soc/consts.py
@@ -5,6 +5,34 @@ def botchify(bekls, lekls):
             continue
         setattr(lekls, attr, 63-getattr(bekls, attr))
 
+
+# Can't think of a better place to put these functions.
+# Return an arbitrary subfield of a larger field.
+def field_slice(start, end):
+    """Answers with a subfield slice of the signal r ("register"),
+    where the start and end bits use IBM conventions.  start < end.
+    The range specified is inclusive on both ends.
+    """
+    if start >= end:
+        raise ValueError(
+            "start ({}) must be less than end ({})".format(start, end)
+        )
+    start = 63 - start
+    end = 63 - end
+    return slice(end, start + 1)
+
+
+def field(r, start, end=None):
+    """Answers with a subfield of the signal r ("register"), where
+    the start and end bits use IBM conventions.  start < end, if
+    end is provided.  The range specified is inclusive on both ends.
+    """
+    if end is None:
+        return r[63 - start]
+    else:
+        return r[field_slice(start, end)]
+
+
 # Listed in V3.0B Book III Chap 4.2.1
 # MSR bit numbers, *bigendian* order (PowerISA format)
 # use this in the simulator
@@ -47,7 +75,7 @@ botchify(MSRb, MSR)
 
 # use this in the simulator
 class PIb:
-    TM_BAD_THING = 42 # 1 for a TM Bad Thing type interrupt
+    TM_BAD_THING = 42    # 1 for a TM Bad Thing type interrupt
     FP           = 43    # 1 if FP exception
     ILLEG        = 44    # 1 if illegal instruction (not doing hypervisor)
     PRIV         = 45    # 1 if privileged interrupt

diff --git a/src/soc/fu/trap/formal/proof_main_stage.py b/src/soc/fu/trap/formal/proof_main_stage.py
index 8767bcede9850cc388fb902e906b5d1226d1547c..823a58f29891bf72b0a612b8488e29b78b459f5c 100644 (file)
--- a/src/soc/fu/trap/formal/proof_main_stage.py
+++ b/src/soc/fu/trap/formal/proof_main_stage.py
@@ -19,7 +19,7 @@ from nmigen.cli import rtlil
 from nmutil.extend import exts
 from nmutil.formaltest import FHDLTestCase
 
-from soc.consts import MSR, MSRb, PI, TT
+from soc.consts import MSR, MSRb, PI, TT, field
 
 from soc.decoder.power_enums import MicrOp
 
@@ -28,22 +28,6 @@ from soc.fu.trap.pipe_data import TrapPipeSpec
 from soc.fu.trap.trap_input_record import CompTrapOpSubset
 
 
-def field(r, start, end=None):
-    """Answers with a subfield of the signal r ("register"), where
-    the start and end bits use IBM conventions.  start < end, if
-    end is provided.  The range specified is inclusive on both ends.
-    """
-    if end is None:
-        return r[63 - start]
-    if start >= end:
-        raise ValueError(
-            "start ({}) must be less than end ({})".format(start, end)
-        )
-    start = 63 - start
-    end = 63 - end
-    return r[end:start+1]
-
-
 class Driver(Elaboratable):
     """
     """

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 6ca37f156693238f22814de7b8ef8834c3fc78f3..1632bfb167b2ba1bdd3f59684f3208acdfdda2aa 100644 (file)
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -19,23 +19,7 @@ from soc.decoder.power_enums import MicrOp
 from soc.decoder.power_fields import DecodeFields
 from soc.decoder.power_fieldsn import SignalBitRange
 
-from soc.consts import MSR, MSRb, PI, TT
-
-
-def field(r, start, end=None):
-    """Answers with a subfield of the signal r ("register"), where
-    the start and end bits use IBM conventions.  start < end, if
-    end is provided.  The range specified is inclusive on both ends.
-    """
-    if end is None:
-        return r[63 - start]
-    if start >= end:
-        raise ValueError(
-            "start ({}) must be less than end ({})".format(start, end)
-        )
-    start = 63 - start
-    end = 63 - end
-    return r[end:start+1]
+from soc.consts import MSR, MSRb, PI, TT, field, field_slice
 
 
 def msr_copy(msr_o, msr_i, zero_me=True):
@@ -258,7 +242,7 @@ class TrapMainStage(PipeModBase):
 
                 # don't understand but it's in the spec.  again: bits 32-34
                 # are copied from srr1_i and need *restoring* to msr_i
-                bits = slice(63-31,63-29+1) # bits 29, 30, 31 (Power notation)
+                bits = field_slice(29, 31)  # bits 29, 30, 31 (Power notation)
                 with m.If((msr_i[bits] == Const(0b010, 3)) &
                           (srr1_i[bits] == Const(0b000, 3))):
                     comb += msr_o.data[bits].eq(msr_i[bits])