blackbox: Include whiteboxed modules

Signed-off-by: gatecat <gatecat@ds0.me>

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 32069ce036519b7ee9df9d51d43c837d2024ff7c..87cbaa0d5379e0dc6e75265f8246e159a9172491 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -808,12 +808,12 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
        return result;
 }
 
-std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
+std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
 {
        std::vector<RTLIL::Module*> result;
        result.reserve(modules_.size());
        for (auto &it : modules_)
-               if (it.second->get_blackbox_attribute())
+               if (it.second->get_blackbox_attribute(include_wb))
                        continue;
                else if (selected_whole_module(it.first))
                        result.push_back(it.second);

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a747b9d3c8a13c784048b7d1abc451136b7ac4b5..bbdf355fa1f4302e83e7fc200521b05d5eb1423d 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1112,7 +1112,7 @@ struct RTLIL::Design
 
        std::vector<RTLIL::Module*> selected_modules() const;
        std::vector<RTLIL::Module*> selected_whole_modules() const;
-       std::vector<RTLIL::Module*> selected_whole_modules_warn() const;
+       std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
 #ifdef WITH_PYTHON
        static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
 #endif

diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
index 08a6355148e07a4d4fcb6bd47fcd6d7641e61683..fca91852c35661429cd454e1a95455cba799f430 100644 (file)
--- a/passes/cmds/blackbox.cc
+++ b/passes/cmds/blackbox.cc
@@ -46,10 +46,11 @@ struct BlackboxPass : public Pass {
                }
                extra_args(args, argidx, design);
 
-               for (auto module : design->selected_whole_modules_warn())
+               for (auto module : design->selected_whole_modules_warn(true))
                {
                        module->makeblackbox();
                        module->set_bool_attribute(ID::blackbox);
+                       module->set_bool_attribute(ID::whitebox, false);
                }
        }
 } BlackboxPass;

diff --git a/tests/various/blackbox_wb.ys b/tests/various/blackbox_wb.ys
new file mode 100644 (file)
index 0000000..f9c9bec
--- /dev/null
+++ b/tests/various/blackbox_wb.ys
@@ -0,0 +1,14 @@
+read_verilog <<EOT
+(* whitebox *)
+module box(input a, output q);
+assign q = ~a;
+endmodule
+
+module top(input a, output q);
+box box_i(.a(a), .q(q));
+endmodule
+EOT
+select -assert-count 1 =box/t:$not
+blackbox =box
+select -assert-count 0 =A:whitebox
+select -assert-count 0 =box/t:$not