makefile for gpio and removing dependent files in gpio
authorNeel <neelgala@gmail.com>
Mon, 16 Jul 2018 06:51:20 +0000 (12:21 +0530)
committerNeel <neelgala@gmail.com>
Mon, 16 Jul 2018 06:51:20 +0000 (12:21 +0530)
src/bsv/bsv_lib/Makefile.gpio.templates [new file with mode: 0644]
src/bsv/bsv_lib/gpio.bsv

diff --git a/src/bsv/bsv_lib/Makefile.gpio.templates b/src/bsv/bsv_lib/Makefile.gpio.templates
new file mode 100644 (file)
index 0000000..8e9060f
--- /dev/null
@@ -0,0 +1,53 @@
+### Makefile for the srio
+
+TOP_MODULE:=mkgpio
+TOP_FILE:=gpio.bsv
+HOMEDIR:=./
+TOP_DIR:=./
+BSVBUILDDIR:=./build/
+VERILOGDIR:=./verilog/
+BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC
+FPGA=xc7a100tcsg324-1
+export HOMEDIR=./
+export TOP=$(TOP_MODULE)
+
+default: full_clean compile link simulate
+
+timing_area: full_clean generate_verilog vivado_build
+
+.PHONY: compile
+compile:
+       @echo Compiling $(TOP_MODULE)....
+       @mkdir -p $(BSVBUILDDIR)
+       @bsc -u -sim -simdir $(BSVBUILDDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) -keep-fires -p $(BSVINCDIR) -g $(TOP_MODULE)  $(TOP_DIR)/$(TOP_FILE)
+       @echo Compilation finished
+
+.PHONY: link
+link:
+       @echo Linking $(TOP_MODULE)...
+       @mkdir -p bin
+       @bsc -e $(TOP_MODULE) -sim -o ./bin/out -simdir $(BSVBUILDDIR) -p .:%/Prelude:%/Libraries:%/Libraries/BlueNoC:./c_files -keep-fires -bdir $(BSVBUILDDIR) -keep-fires ./c_files/checker.c    
+       @echo Linking finished
+
+.PHONY: generate_verilog 
+generate_verilog:
+       @echo Compiling $(TOP_MODULE) in verilog ...
+       @mkdir -p $(BSVBUILDDIR); 
+       @mkdir -p $(VERILOGDIR); 
+       @bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR)\
+  $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout\
+  -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE)  || (echo "BSC COMPILE ERROR"; exit 1) 
+
+.PHONY: simulate
+simulate:
+       @echo Simulation...
+       ./bin/out 
+       @echo Simulation finished. 
+
+.PHONY: clean
+clean:
+       rm -rf build bin *.jou *.log
+
+.PHONY: full_clean
+full_clean: clean
+       rm -rf verilog fpga
index 4aadfd2c24cb8b3a641200ed7b331d5117cfd622..cf44bd42ca00bb5ebdbda85f91b92d99531b449e 100644 (file)
@@ -19,11 +19,14 @@ package gpio;
        import ConfigReg                        ::*;
        /*============================ */
        /*===== Project Imports ===== */
-       `include "defined_parameters.bsv"
        import Semi_FIFOF        :: *;
        import AXI4_Lite_Types   :: *;
-       import AXI4_Lite_Fabric  :: *;
        /*============================ */
+  `define ADDR 32
+  `define DATA 64
+  `define USER 0
+  `define IONum 32
+  `define GPIO_MUX
 
        interface GPIO;
                (*always_ready,always_enabled*)
@@ -43,7 +46,7 @@ package gpio;
            `ifdef GPIO_MUX
                method Vector#(`IONum,Bit#(2))   gpio_MUX;
            `endif
-               interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) axi_slave;
+               interface AXI4_Lite_Slave_IFC#(`ADDR,`DATA,`USER) axi_slave;
        endinterface
 
        (*synthesize*)
@@ -65,7 +68,7 @@ package gpio;
                  Vector#(`IONum,ConfigReg#(Bit#(2))) muxer_reg                                 <-replicateM(mkConfigReg(0));
          `endif
                
-               AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
+               AXI4_Lite_Slave_Xactor_IFC #(`ADDR, `DATA, `USER)  s_xactor <- mkAXI4_Lite_Slave_Xactor;
     let ionum=valueOf(`IONum);
                rule capture_interrupt;
                        for(Integer i=0;i<`IONum;i=i+1)
@@ -129,7 +132,7 @@ package gpio;
                rule rl_rd_respond;
                        let ar<- pop_o(s_xactor.o_rd_addr);
                        Bit#(32) temp=0;
-                       AXI4_Lite_Rd_Data#(`Reg_width,`USERSPACE) r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
+                       AXI4_Lite_Rd_Data#(`DATA,`USER) r = AXI4_Lite_Rd_Data {rresp: AXI4_LITE_OKAY, rdata: ?, ruser: 0};
                        if(ar.araddr[5:0]=='h0)begin
                                for(Integer i=0;i<`IONum;i=i+1)
                                        temp[i]=pack(direction_reg[i]);