use p.i_valid in core instead of explicit signal ivalid_i

converting core to Pipeline API

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index a0c4a816944c3b5e592649a13d89872106eb2e50..a36fc92ac480e4ed01fd5eb82c9ac9a65c9511c3 100644 (file)
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -91,7 +91,6 @@ class CoreInput:
             self.sv_pred_dm = Signal() # TODO: SIMD width
 
         # issue/valid/busy signalling
-        self.ivalid_i = Signal(reset_less=True) # instruction is valid
         self.issue_i = Signal(reset_less=True)
 
     def eq(self, i):
@@ -100,6 +99,7 @@ class CoreInput:
         self.state.eq(i.state)
         self.raw_insn_i.eq(i.raw_insn_i)
         self.bigendian_i.eq(i.bigendian_i)
+        self.issue_i.eq(i.issue_i)
         if not self.svp64_en:
             return
         self.sv_rm.eq(i.sv_rm)
@@ -277,12 +277,13 @@ class NonProductionCore(ControlBase):
             sync += counter.eq(counter - 1)
             comb += busy_o.eq(1)
 
-        with m.If(self.i.ivalid_i): # run only when valid
+        with m.If(self.p.i_valid): # run only when valid
             with m.Switch(self.i.e.do.insn_type):
                 # check for ATTN: halt if true
                 with m.Case(MicrOp.OP_ATTN):
                     m.d.sync += self.o.core_terminate_o.eq(1)
 
+                # fake NOP - this isn't really used (Issuer detects NOP)
                 with m.Case(MicrOp.OP_NOP):
                     sync += counter.eq(2)
                     comb += busy_o.eq(1)

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index d208e1c220568a8b627d1876d582a417439917b0..e917756e187bf7150e291994f7c8c2a66c266f45 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -867,7 +867,7 @@ class TestIssuerInternal(Elaboratable):
 
         # temporaries
         core_busy_o = ~core.p.o_ready                # core is busy
-        core_ivalid_i = core.i.ivalid_i             # instruction is valid
+        core_ivalid_i = core.p.i_valid              # instruction is valid
         core_issue_i = core.i.issue_i               # instruction is issued
         insn_type = core.i.e.do.insn_type           # instruction MicroOp type