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Implement a 1W/1R register file, XOR style
authorCesar Strauss <cestrauss@gmail.com>
Sun, 17 Apr 2022 22:27:58 +0000 (19:27 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 17 Apr 2022 22:41:06 +0000 (19:41 -0300)
Test case seems to be working.
Total 6x 1RW SRAMs were used, but no DFF RAM was needed.
Still needs a bypass for a transparent read option.


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