Merge pull request #29 from JiaoXianjun/master

Openwifi stand front page update

diff --git a/content/stands/openwifi.md b/content/stands/openwifi.md
index 2e376360fd1ba3174fc10a69acc6633c6d6e3379..cb450853dce76cb456b3b74e428a2cc159a97e41 100644 (file)
--- a/content/stands/openwifi.md
+++ b/content/stands/openwifi.md
@@ -1,37 +1,47 @@
 ---
-description: "openwifi: opensource WiFi chip!\r\n\r\nFeatures:\r\n802.11a/g/n\r\n\
-  20MHz bandwidth; 70 MHz to 6 GHz frequency range\r\nMode tested: Ad-hoc; Station;\
-  \ AP, Monitor\r\nDCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)\r\n\
-  Configurable channel access priority parameters:\r\n    duration of RTS/CTS, CTS-to-self\r\
-  \n    SIFS/DIFS/xIFS/slot-time/CW/etc\r\nTime slicing based on MAC address\r\nEasy\
-  \ to change bandwidth and frequency:\r\n    2MHz for 802.11ah in sub-GHz\r\n   \
-  \ 10MHz for 802.11p/vehicle in 5.9GHz\r\nCSI (Channel State Information, freq offset,\
-  \ equalizer to computer)\r\nIQ capture (real-time AGC, RSSI, IQ sample to computer)\r\
-  \nOn roadmap: 802.11ax"
+description: |
+  <p>openwifi: opensource WiFi chip!</p>
+  <ul>
+    <li>802.11a/g/n</li>
+    <li>20MHz bandwidth; 70 MHz to 6 GHz frequency range</li>
+    <li>Mode tested: Ad-hoc; Station; AP, Monitor</li>
+    <li>DCF (CSMA/CA) low MAC layer in FPGA (10us SIFS is achieved)</li>
+    <li>802.11 packet injection</li>
+    <li>CSI (Channel State Information, freq offset, equalizer to computer)</li>
+    <li>IQ capture (real-time AGC, RSSI, IQ sample to computer)</li>
+    <li>Configurable channel access priority parameters: duration of RTS/CTS, CTS-to-self, SIFS/DIFS/xIFS/slot-time/CW/etc</li>
+    <li>Time slicing based on MAC address (time gated/scheduled FPGA queues)</li>
+    <li>Easy to change bandwidth and frequency: 2MHz for 802.11ah (sub-GHz); 10MHz for 802.11p/vehicle (5.9GHz)</li>
+    <li>On roadmap: 802.11ax</li>
+  </ul>
 layout: stand
 logo: stands/openwifi/logo.png
-new_this_year: "1. Port the design from a single type of board to 6 types of boards!\
-  \ From high end (expensive) to low end (cheap for entry)\r\n2. Low latency ping:\
-  \ 200~300us round trip.\r\n3. Important improvement on stability and performance.\r\
-  \n4. Increase the packet queue from 2 to 4 in FPGA, meet the Linux mac80211 requirement/assumption\
-  \ better.\r\n5. Channel estimation and bug fix on the OFDM receiver. Better reception\
-  \ performance.\r\n6. CSI (Channel State Information) interface to Linux. And it\
-  \ doesn't affect normal WiFi communication.\r\n7. IQ sample interface to Linux.\
-  \ And it doesn't affect normal WiFi communication.\r\n8. Low cost SDR openwifi dongle\
-  \ (<100usd) and chip tape out plan are under preparation. Stay tuned!"
+new_this_year: |
+  <p>We have updates across our projects since FOSDEM'20:</p>
+  <ul>
+    <li>802.11n (WiFi4)!</li>
+    <li>Port the design from a single type of FPGA dev board to 6 types of boards! From high end (as expensive as 3600USD) to low end (900USD).</li>
+    <li>Low latency ping RTT (Round Trip Time): 200~300us.</li>
+    <li>Essential improvement on stability, 802.11 compatibility and performance cross FPGA and Linux driver.</li>
+    <li>Increase the FPGA packet queue from 2 to 4, meet the Linux mac80211 requirement/assumption about QoS/Priority-strategy better.</li>
+    <li>Channel estimation and frequency offset compensation bug fix on the OFDM receiver. Better reception performance.</li>
+    <li>CSI (Channel State Information) interface from FPGA to Linux. And it doesn't affect normal WiFi communication.</li>
+    <li>IQ sample interface from FPGA to Linux. And it doesn't affect normal WiFi communication.</li>
+    <li>Open the idea to Low cost SDR openwifi dongle (+/-200USD) and real chip tape out!</li>
+  </ul>
 showcase: "All of those opensource hardware projects are focusing on the CPU side:\r\
   \nRISC-V, all kinds of open CPU cores, Raspberry PI, xxxx PI, PINE64, openWRT, AI/machine-learning\
   \ accelerators.\r\nHowever the radio connectivity part of those opensource hardware\
   \ boards are still from black-box silicon (commercial chips, like WiFi chips from\
-  \ big companies).\r\nOpenwifi project, which was announced in the last FOSDEM, is\
+  \ big companies).\r\nOpenwifi project, which was announced in the FOSDEM'20, is\
   \ the first attempt to build an opensource chip in the radio connectivity domain!\r\
   \nNow we have tested the design on the FPGA development board (SDR -- Software Defined\
   \ Radio), and it works well in the real world scenario. Meanwhile we also add some\
   \ unique features that commercial chips don't have.\r\n\r\nWe hope more people can\
   \ come and think about the opensource activity in the radio chip domain, and invest\
-  \ more in this domain!\r\n\r\nWe are also eager to hear from people about the idea\
-  \ (under internal preparation): Low cost SDR openwifi dongle (<100usd) and chip\
-  \ tape out plan."
+  \ more in this domain!\r\n\r\nWe are also eager to seek people's voice and help about\
+  \ the idea of: Low cost SDR openwifi dongle (+/-200usd) and chip\
+  \ tape out!"
 themes:
 - Hardware
 title: openwifi