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submodule tidyup
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 7 Dec 2021 01:06:04 +0000 (01:06 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 7 Dec 2021 12:11:41 +0000 (12:11 +0000)
src/soc/experiment/dcache.py patch | blob | history

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 60e06c11c3653077bf40bae76cf15821e890a8b4..180fa10dd423be1d6a65a00cdf652add65c2b3ff 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -1231,7 +1231,7 @@ class DCache(Elaboratable):
             d_out   = Signal(WB_DATA_BITS, name="dout_%d" % i) # cache_row_t
 
             way = CacheRam(ROW_BITS, WB_DATA_BITS, ADD_BUF=True, ram_num=i)
-            setattr(m.submodules, "cacheram_%d" % i, way)
+            m.submodules["cacheram_%d" % i] = way
 
             comb += way.rd_en.eq(do_read)
             comb += way.rd_addr.eq(rd_addr)